Boosting a voltage

[Peter]

I want to daisy-chain a string of 74HC595 shift registers over a long
distance (hundreds of feet in total). By the time the signals gets to
the end the voltages will probably be below the minimum threshold for
"hi". I need to boost 3 signals (data, clock and latch). I can do it
with a 74HC27 triple OR gate (powered from 5v locally). What I want to
know is whether there is any 8-pin chip that I can use to achieve the
same thing?

 

[Winfield Hill]

Peter wrote...

I want to daisy-chain a string of 74HC595 shift registers over a long
distance (hundreds of feet in total). By the time the signals gets to
the end the voltages will probably be below the minimum threshold for
"hi". I need to boost 3 signals (data, clock and latch). I can do it
with a 74HC27 triple OR gate (powered from 5v locally). What I want
to know is whether there is any 8-pin chip that I can use to achieve
the same thing?

You may not need to speed up the data line, because at each clock
transition the shift register takes the data value *before* the
clock, i.e. just *after* the previous clock. As for the clock
and latch lines, there are lots of 8-pin dual MOSFET drivers that
can handle the task, with low-Z rail-to-rail outputs.

One piece of advice, to insure there's no trouble with the clock
and data lines, add a 1/5-clock RC delay after each chip's data
output before the next chip's data input. Another nugget, add a
static-protection network to each input in this distributed mess.

Thanks,
- Win

whill_at_picovolt-dot-com

 

[Peter]

Winfield Hill <Winfield_member@newsguy.com> wrote in message >

You may not need to speed up the data line, because at each clock
transition the shift register takes the data value *before* the
clock, i.e. just *after* the previous clock. As for the clock
and latch lines, there are lots of 8-pin dual MOSFET drivers that
can handle the task, with low-Z rail-to-rail outputs.

One piece of advice, to insure there's no trouble with the clock
and data lines, add a 1/5-clock RC delay after each chip's data
output before the next chip's data input. Another nugget, add a
static-protection network to each input in this distributed mess.

Do you have an example of a part number for the dual mosfet driver please?
What sort of trouble are you talking about re the RC delay?
What is a static protection "network"?

 

[Winfield Hill]

Peter wrote...

Winfield Hill wrote,
You may not need to speed up the data line, because at each clock
transition the shift register takes the data value *before* the
clock, i.e. just *after* the previous clock. As for the clock
and latch lines, there are lots of 8-pin dual MOSFET drivers that
can handle the task, with low-Z rail-to-rail outputs.

One piece of advice, to insure there's no trouble with the clock
and data lines, add a 1/5-clock RC delay after each chip's data
output before the next chip's data input. Another nugget, add a
static-protection network to each input in this distributed mess.

Do you have an example of a part number for the dual mosfet
driver please?

For example the Microchip TC4427A, operating from 5V supplies.

http://www.microchip.com/1010/pline/analog/anicateg/power/mosfet/tc4_46/tc4427/
http://www.microchip.com/download/lit/pline/analog/power/mosfet/21422b.pdf

What sort of trouble are you talking about re the RC delay?

For short links, or any length where the clock risetime is
slowed a bit, it's important to delay the data a just bit,
to be sure the clock can't inadvertantly sample *after* the
data change from the previous stage. One vulnerability
occurs because two shift register chips may have different
clock thresholds.

What is a static protection "network"?

A series resistor, followed by diodes to supply and ground
(optional), plus a small cap to gnd (optional), and a 2nd
series resistor (optional).

Thanks,
- Win

whill_at_picovolt-dot-com