boolean to std_logic

[valentin tihomirov]

Is there any standard package that can convert TRUE to '1' and FALSE to '0'?
Should I write my function? Why there isn't implicit sythax of that?

 

[Ray Andraka]

This is actually a spin-off of a topic that is being discussed in the VHDL
standards committee. The rub is that True does not always equate to
'1'..negative logic systems use '0' = true. A function to do this is
straight-forward to write.

valentin tihomirov wrote:

Is there any standard package that can convert TRUE to '1' and FALSE to '0'?
Should I write my function? Why there isn't implicit sythax of that?

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759

 

[David R Brooks]

"valentin tihomirov" <valentinNOSPAM@abelectron.com> wrote:

:Is there any standard package that can convert TRUE to '1' and FALSE to '0'?
:Should I write my function? Why there isn't implicit sythax of that?
:

There are a number of standard functions for this, in the various
libraries.
Example: ieee.numeric_extra.to_std_logic()

There isn't "implicit syntax" because VHDL is a strongly-typed
language. You can only change one type to another explicitly. (Some
day, that will save your life

 

[valentin tihomirov]

Thanks. I've got a more general answer regarding VHDL. VHDL is a strongly
typed language; thus, all the type conversions should be explicit. It should
save one's life, some day. In addition, I've discovered a Boolean type that
makes code much cleaner allowing to bypass the conversion in most cases.

 

[Mike Treseler]

valentin tihomirov wrote:

Is there any standard package that can convert TRUE to '1' and FALSE to '0'?
Should I write my function?

yes:

http://groups.google.com/groups?q=vhdl+active_high

-- Mike Treseler