board delay impementation in verilog

[Arvind]

Hi,
I am having a scenario where ASIC IO's are talking to memory IO's. Both
the IO's are BIDI.
I want to simulate the interconnect between two side IO's with some
static delays in verilog .
I had tried using wire delays but it also stops working when change in
signal frequency becomes more then the propagation delay used in wire
(because of inertial delay phenomena).

Is there any better way of simulating this scanario ?

Regards,
-Arvind