blocking with intra delay

[am.imak@gmail.com]

Hi folks,

I am newbie to verilog from vhdl background. So,please help me in
getting through blocking & nonblocking.

Is a <= #1 b; and
a = #1 b; are same . I am not able to see any diffrence.

That means if intra delays are used then there is no difference
between blocking & nonblocking.

Thanks for your comments.

 

[raul]

Hi,

What tool are you using to simulate your design?

RAUL

 

[Art Stamness]

No they are very different type of assignments. Registers (flip flops,
latches) should be modeled using Non-blocking <= assignments. Memories,
Clocks and Combinational Logic should be modeled using the blocking
assignments ( Generally, there are always exceptions ).

Here is where you will see the difference. In the below example, There
is a pipeline of registers. There is an evalutaion phase, and an
assignment phase, so the values for div_2, pipe_a, and pipe_b, are all
read at one time, and then the assignment occurs later. This means you
will see a pipeline behavior down the pipe_* signals ( this will look
like stairs on a waveform viewer).

There is also an example using a blocking assignment, where the
evaluation is immediately followed by the assignment. So when the line
of code "mem_a = div_2 ; " evaluates, immediately the value of mem_a is
updated. So when the next line of code executres "mem_b = mem_a", it
gets the new value of mem_a. So on a waveform viewer you will see
mem_c, mem_b, and mem_a all change at te same time, and you won't see
any stair pattern.

-Art


module foo () ;

reg clk ;
reg div_2 ;
reg pipe_a, pipe_b, pipe_c ;
reg mem_a, mem_b, mem_c ;

initial begin
div_2 = 1'b0 ;
clk = 1'b0 ;
end

forever #5 clk = ~clk ;

// Divide by 2 pattern generator
always @(negedge clk ) div_2 = ~div_2 ;

always @(posedge clk )
begin
pipe_a <= div_2 ;
pipe_b <= pipe_a ;
pipe_c <= pipe_b ;
end

always @(posedge clk )
begin
mem_a = div_2 ;
mem_b = mem_a ;
mem_c = mem_b ;
end

endmodule

 

[am.imak@gmail.com]

I think tool is irrelavent to my question.

 

[am.imak@gmail.com]

Hi ,

No they are very different type of assignments. > Registers (flip flops,
tches) should be modeled using Non-blocking > <= assignments. Memories,
Clocks and Combinational Logic should be
modeled using the blocking
assignments ( Generally, there are always
exceptions ).

My question was that both the assignmens would take place after 1 unit
of time, if intra delay is used.

Suppose I have two concurrent assignments with intra delay from
different procedural blocks, then wchich would simulate first(blocking
or nonblocking).

 

[Art Stamness]

So yeah, I should have explained more. There will be a difference. Say
you have :

always @(posedge clk)
`ifdef NON_BLOCKING
foo <= #1 bar ;
`else
foo = #1 bar ;

always @(posedge clk)
begin
#1 ;
$display ("Foo is %b at %d", foo, $time );
end

When using the non-blocking assignments. You will always see the *old*
value of foo displayed. If you use the blocking assignment, you have a
race condition, as both threads of execution ( always @ blocks ), are
scheduled to start at the same time, and there order of evaluation will
change the result. If foo update executes first the display will be
the new value, if foo update executes second it will be the old value.
Read : Race condition.

All that said, if you are modeling flop delay, use non-blocking. If you
are modeling combinational logic delay use blocking.

-Art

 

[Art Stamness]

blocking always assigns its values before non-blocking ( within a given
time slice ).

Why don't you explain what type of behavior you are seeking to
simulate, it might aid in the discussion.

-Art