blocking -nonblocking with RHS delay que.

[K.Hemanth]

Hello All,
I have question on usign blocking and nonblocking statement with
delayes.


time: 10 20 30 33 36 45
___________ _____ __________
a ____| |___________| |____| |_______

====================
CASE 1:
always @(a)
out1 = # 5 a;
====================
CASE 2:
always @(a)
out2 <= #5 a;
====================

QUE: Here in case 1, the out1 signal is not exactly as the signal
a.(Part of the signal is missed where signal change stable less then
the delay value)
while in case 2 the out2 signal is exactly the same as the signal a
with delay of 5 time unit.

Can any one exaplain the reason behind it in deatil ?
Should I consider that if I put the delay with blocking (RHS side) it
means, it will block the signal evaluation till 5 time unit ? While
with nonbloking , it won't stops the evaluaion of signal and keeps on
evaluation whenever there is a chagne in sensitivity list?

With Regards,
K.Hemnatha

 

[Jonathan Bromley]

On 13 Jun 2006 11:49:34 -0700, "K.Hemanth"
<hemanth_asic04@yahoo.co.in> wrote:

Hemanth,

I think you have the right idea.

Both your examples use "intra-assignment delay".

The first one

out1 = #5 a;

is easier to understand, but less useful. It is equivalent
to

begin
temporary = a;
#5 out1 = temporary;
end

So execution of the always block stalls for 5 time units, which means
that you can miss another transition on "a" because your code is
not waiting at the @(a) timing control.

By contrast,

out2 <= #5 a;

is much more useful. It computes the value of the right-hand side
(just "a" in your case), then schedules that value to be assigned to
out2 after 5 time units; but then *execution continues immediately*.
Consequently, the always block loops around to the @(a) timing
control immediately, and you don't miss any input transitions.

Note that this gives you TRANSPORT delay (pure time delay), whereas
in VHDL the equivalent statement

out2 <= a after 5 ns;

defaults to INERTIAL delay. VHDL can give the same effect as
Verilog by qualifying the assignment:

out2 <= transport a after 5 ns;

If you want inertial delay in Verilog, you need to use continuous
assignment delay:

wire out3;
assign #5 out3 = a;

or net delay:

wire #5 out4;
assign out4 = a;

hth
--
Jonathan Bromley, Consultant

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are not the views of Doulos Ltd., unless specifically stated.

Hello All,
I have question on usign blocking and nonblocking statement with
delayes.


time: 10 20 30 33 36 45
___________ _____ __________
a ____| |___________| |____| |_______

====================
CASE 1:
always @(a)
out1 = # 5 a;
====================
CASE 2:
always @(a)
out2 <= #5 a;
====================

QUE: Here in case 1, the out1 signal is not exactly as the signal
a.(Part of the signal is missed where signal change stable less then
the delay value)
while in case 2 the out2 signal is exactly the same as the signal a
with delay of 5 time unit.

Can any one exaplain the reason behind it in deatil ?
Should I consider that if I put the delay with blocking (RHS side) it
means, it will block the signal evaluation till 5 time unit ? While
with nonbloking , it won't stops the evaluaion of signal and keeps on
evaluation whenever there is a chagne in sensitivity list?

With Regards,
K.Hemnatha