blocking assignment in synch

Hi

I've have been reading about (non)blocking assignment. The following is
good explanations about their behaviors. However, I still don't
understand this:
why all the emphasis on "blocking assignment is for simulation" and
"non-blocking assignment is for synthesis"? What if the blocking
assignment behavior is what we want for both simulation and synthesis?
Do I not get the correct behavior if using blocking assignment after
synthesis from our chip or fpga? Thanks.

// ------------- from some earlier posts
-----------------------------------
Thit Siriboon wrote:

Hi,
In verilog code x=b+c; d=x+e; reg d will get the "new" value of
x which
I think the synthesis circuit will be output of adder (b+c) go into
the
input of other adder which output is x .
However, I cannot figgure out the systhesis circuit of x<=b+c;
d<=x+e; .
What is it look like?
Thank you
Thit.

1. x=b+c; d=x+e;

This is blocking assignment. This code is modelled like this:

always @(posedge clock)
begin
x = b + c;
d = x + e;
end

This synthesis output would be:

c -----|\ x ____

+>-------|\ | |
b -----|/ >+>---| FF |------ d

|--|/ | |
e ------------| |--|> |
| |____|
|
clock --------------|

The commands are executed in sequential. D is dependent upon x. So
at a clock event all the sequential commands are executed in
sequence.

2. x<=b+c d<=x+e

This non-blocking assignment. This code is modelled like this:

always @(posedge clock)
begin
x <= b + c;
d <= x + e;
end

c -----|\ ____ x ____

+>----| |-------|\ | |
b -----|/ | FF | >+>---| FF |------ d

| | |--|/ | |
|--|> | | |--|> |
| |____| e | |____|
| |
clock -----+------------------|

The commands are executed in parallel. These commands are totally
independent upon their results of each other. So, their event
execution
is performed by independent registers. Following code is exactly the
same as the above

always @(posedge clock) x <= b + c;
always @(posedge clock) d <= x + e;

This coding can be done in one always block only with non-blocking
assignments. The event execution of the Verilog code does not "block"
the others.

Blocking assignments are used to model testbenches, and it is the
basis
of hw/sw co-simulation. Non-blocking assignments are used for
synthesizable
circuits. Always model your hardware with non-blocking assigments.
Always
model your testbench with blocking assignments.

Utku

--
I feel better than James Brown.