Blocking and non blocking assignment in VHDL

[Hendra Gunawan]

Hi folks,
In Verilog, we have blocking and non blocking assignments. Is there any
equivalent assignment in VHDL? From my understanding, inside the "process",
statements are executed consecutively. Is there anyway that I can make it
concurrent, just like the one in Verilog when we use "<=" assignment to
ensure concurrent execution of all the statements in the always block?
Thanks!

Hendra

 

[Allan Herriman]

On Wed, 7 Apr 2004 21:08:44 -0700, "Hendra Gunawan"
<u1000393@email.sjsu.edu> wrote:

Hi folks,
In Verilog, we have blocking and non blocking assignments. Is there any
equivalent assignment in VHDL?

In VHDL, we have blocking and non blocking assignments that are
roughly equivalent to the Verilog ones.

There is a major difference though: All assignments to signals (with
'<=' ) are non blocking (i.e. they happen some (delta) time in the
future), and all assignments to variables (with ':=' )are blocking
(i.e. they happen immediately).

Signals are like regs or wires, depending on context.
Variables are like regs.

Variables (mostly) can only be declared within processes, and have a
scope that is restricted to that process.

From my understanding, inside the "process",
statements are executed consecutively. Is there anyway that I can make it
concurrent, just like the one in Verilog when we use "<=" assignment to
ensure concurrent execution of all the statements in the always block?

Yes, if you use signals, this will happen automatically.

Also, since variables can only be used in the process in which they
are defined, a major possible cause of races has been eliminated.

Regards,
Allan.