Block Ram Problem

[Tim O' Sullivan]

Hi All,

I am a relative novice to vhdl and would really appreciate any
help with this problem. I am trying to construct a simple circuit
which would allow me to pass data from one block Ram on a Xilinx board
to another block Ram. My problem is that although the design
synthesized fine, the data does not show up on the destination block
Ram. The code is attached below. Thanks in advance for any help.
Cheers,

Tim.

--**************VHDL CODE******************


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

library UNISIM;
use UNISIM.VComponents.all;

entity example1 is
port (clk: IN std_logic;
dout: out std_logic_vector(7 downto 0));
end example1;

architecture arch of example1 is

component first_bram
port (addr: IN std_logic_VECTOR(7 downto 0);
clk: IN std_logic;
dout: OUT std_logic_VECTOR(7 downto 0));
end component;

component second_bram
port (addr: IN std_logic_VECTOR(7 downto 0);
clk: IN std_logic;
din: IN std_logic_VECTOR(7 downto 0);
dout: OUT std_logic_VECTOR(7 downto 0);
en: IN std_logic;
we: IN std_logic);
end component;

component my_counter
port (Q: OUT std_logic_VECTOR(7 downto 0);
CLK: IN std_logic);
end component;

signal intermediate_output : std_logic_vector(7 downto 0);
signal counter_address : std_logic_vector(7 downto 0);
signal writeEnable : std_logic := '1';

begin

my_counter1 : my_counter port map(Q => counter_address, CLK => clk);
bram1 : first_bram port map (addr => counter_address, clk => clk,
dout => intermediate_output);
bram2 : second_bram port map (addr => counter_address, clk => clk,
din => intermediate_output, dout => dout, en => '1', we =>
writeEnable);
end arch;

 

[Mike Treseler]

Tim O' Sullivan wrote:

My problem is that although the design
synthesized fine, the data does not show up on the destination block
Ram.

Keep in mind that a null architecture will "synthesize fine".

Learning to use VHDL simulation may take a long time,
but debugging synthesis by trial and error may take
even longer.

-- Mike Treseler