Block Ram clocks

[RobertP]

I'm using block rams to create FIFOs in Virtex II device.And mapper
report problem with using clock, that drives these block rams:


WARNING:LIT:175 - Clock buffer is designated to drive clock loads. BUFGMUX
symbol "clock_reset_clk80_bufg" (output signal=clk) has a mix of
clock and
non-clock loads. Some of the non-clock loads are (maximum of 5 listed):
Pin CLKA of txfifo1_bram3
Pin CLKB of txfifo1_bram3
Pin CLKA of txfifo1_bram2
Pin CLKB of txfifo1_bram2
Pin CLKA of txfifo1_bram1



I'm a little suprised, because I thought that these ARE clock loads.
Should I worry about that?
Any other comments?

--
Robert Pudlik

 

[RobertP]

I forgot: I'm using ISE5.2 with the latest service pack, and XST for
synthesis.


RobertP wrote:

I'm using block rams to create FIFOs in Virtex II device.And mapper
report problem with using clock, that drives these block rams:


WARNING:LIT:175 - Clock buffer is designated to drive clock loads. BUFGMUX
symbol "clock_reset_clk80_bufg" (output signal=clk) has a mix of
clock and
non-clock loads. Some of the non-clock loads are (maximum of 5 listed):
Pin CLKA of txfifo1_bram3
Pin CLKB of txfifo1_bram3
Pin CLKA of txfifo1_bram2
Pin CLKB of txfifo1_bram2
Pin CLKA of txfifo1_bram1



I'm a little suprised, because I thought that these ARE clock loads.
Should I worry about that?
Any other comments?

--
Robert Pudlik

 

[Barry Brown]

And I get the same warning for clocked multiplier blocks. I suspect the
mapper is goofy.

Barry Brown


"RobertP" <rpudlik@poczta.onet.pl> wrote in message
news:bn5l71$d8e$2@news.onet.pl...

I forgot: I'm using ISE5.2 with the latest service pack, and XST for
synthesis.


RobertP wrote:

I'm using block rams to create FIFOs in Virtex II device.And mapper
report problem with using clock, that drives these block rams:


WARNING:LIT:175 - Clock buffer is designated to drive clock loads.
BUFGMUX
symbol "clock_reset_clk80_bufg" (output signal=clk) has a mix of
clock and
non-clock loads. Some of the non-clock loads are (maximum of 5
listed):
Pin CLKA of txfifo1_bram3
Pin CLKB of txfifo1_bram3
Pin CLKA of txfifo1_bram2
Pin CLKB of txfifo1_bram2
Pin CLKA of txfifo1_bram1



I'm a little suprised, because I thought that these ARE clock loads.
Should I worry about that?
Any other comments?

--
Robert Pudlik