blif2vst - Cannot get full vhdl

[Ashutosh Chakraborty]

Ciao,

I am running into a problem converting my blif file into vhdl. I run
blif2vst as follows

blif2vst H9.genlib normal_flow.blif normal_flow.vhd

What I get out of this is a very skeleton VHDL having just a empty
module block. What am I doing wrong? It expects the library in the
genlib format right?

regards,
Ashutosh