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Hi, I'm writing a little component in vhdl and I need to use real
values in it. Since I can't synthesize a componet that has real ports,
I must convert a 64 std_logic_vector from and to real. I already found
a function real2bits, but I also need a sort of bits2real.
Anyone help?
values in it. Since I can't synthesize a componet that has real ports,
I must convert a 64 std_logic_vector from and to real. I already found
a function real2bits, but I also need a sort of bits2real.
Anyone help?