bit width truncation warning

[BERT]

Hi,

I am a relative newbie to verilog. I am trying to write a parameterized
module, where I have declared a register as:

parameter pmW = 4;
reg [pmW-1:0] pmReg;

Now, I want to initialize this register using:

pmReg <= 0;

(as the bit-width is parameterized, and I also can't write something
like pmW'b0 or similar in verilog).

When, I try to synthesize the design in Altera Quartus II, I get a
warning for the above line that I am trying to truncate a 32-bit value
to a 4 bit value. So, I have two questions:

1. Since "0" is a constant, shouldn't the compiler recognize during
compile time that it will fit in a four-bit register.

2. I can remove the compiler warning using two methods:

a) by defining a parameter "zero" as:

parameter zero = 0;
pmReg <= zero[pmW-1:0];

b) re-writing the above line as:

pmReg <= 1'b0;

In either case, I feel this is completely unnecessary. Or, am I barking
up the wrong tree. (i.e.,) this is specific to the Altera Quartus
compiler ??

Thanks for any insight.

Thanks,
Vijay.

 

[Swapnajit Mitra]

BERT wrote:

Hi,

I am a relative newbie to verilog. I am trying to write a parameterized
module, where I have declared a register as:

parameter pmW = 4;
reg [pmW-1:0] pmReg;

Now, I want to initialize this register using:

pmReg <= 0;

(as the bit-width is parameterized, and I also can't write something
like pmW'b0 or similar in verilog).

When, I try to synthesize the design in Altera Quartus II, I get a
warning for the above line that I am trying to truncate a 32-bit value
to a 4 bit value. So, I have two questions:

1. Since "0" is a constant, shouldn't the compiler recognize during
compile time that it will fit in a four-bit register.

2. I can remove the compiler warning using two methods:

a) by defining a parameter "zero" as:

parameter zero = 0;
pmReg <= zero[pmW-1:0];

b) re-writing the above line as:

pmReg <= 1'b0;

In either case, I feel this is completely unnecessary. Or, am I barking
up the wrong tree. (i.e.,) this is specific to the Altera Quartus
compiler ??

Thanks for any insight.

Thanks,
Vijay.

o An integer in Verilog is defined as a 32-bit quantity. Hence the
warning.
o Your solution (b) actually has another issue (though sounds like
altera did not mind), since what you are really doing there is:
pmReg <= {3'bx, 1'b0};

- Swapnajit.
--
SystemVerilog, DPI, Verilog PLI and all other good stuffs.
Project VeriPage: http://www.project-veripage.com
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[Ajeetha]

Vijay,
Use Verilog's repetition operator for this:

pmReg <= pmW{1'b0};

HTH
Ajeetha, CVC
www.noveldv.com

 

[BERT]

Ajeetha wrote:

Vijay,
Use Verilog's repetition operator for this:

pmReg <= pmW{1'b0};

Thanks for your suggestions folks ! Actually, I am surprised because:

pmReg <= 1'b0

seems to work fine (i.e., sets the register to all zeros). No
complaints from Altera and the program worked exactly how I wanted (I
have used this type of assignment in other places too).

Thanks,
Vijay.

 

[Stephen Williams]

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Swapnajit Mitra wrote:

BERT wrote:
Hi,

I am a relative newbie to verilog. I am trying to write a parameterized
module, where I have declared a register as:

parameter pmW = 4;
reg [pmW-1:0] pmReg;

Now, I want to initialize this register using:

pmReg <= 0;

(as the bit-width is parameterized, and I also can't write something
like pmW'b0 or similar in verilog).

When, I try to synthesize the design in Altera Quartus II, I get a
warning for the above line that I am trying to truncate a 32-bit value
to a 4 bit value.

o An integer in Verilog is defined as a 32-bit quantity. Hence the
warning.

Not strictly correct. An unsigned integer has no specific size.
The standard only says that an implementation must carry at least
32bits of an entered number. The standard gives implementers plenty
of latitude to do the Right Thing(tm) here.

o Your solution (b) actually has another issue (though sounds like
altera did not mind), since what you are really doing there is:
pmReg <= {3'bx, 1'b0};

Absolutely not. The right side of "foo[31:0] = 1'b0" will be padded
with zeros according to Verilog padding rules.


- --
Steve Williams "The woods are lovely, dark and deep.
steve at icarus.com But I have promises to keep,
http://www.icarus.com and lines to code before I sleep,
http://www.picturel.com And lines to code before I sleep."
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Ajeetha wrote:

Use Verilog's repetition operator for this:

pmReg <= pmW{1'b0};

You need an extra set of curly braces for this:

pmReg <= {pmW{1'b0}};

 

BERT wrote:

Thanks for your suggestions folks ! Actually, I am surprised because:

pmReg <= 1'b0

seems to work fine (i.e., sets the register to all zeros). No
complaints from Altera and the program worked exactly how I wanted (I
have used this type of assignment in other places too).

It should work fine. It should extend the value with zeroes up to the
desired width. The only reason to use a replication is if you need a
value of an exact width, with no truncation and no extension.

 

[Chris F Clark]

BERT wrote:

Thanks for your suggestions folks ! Actually, I am surprised because:

pmReg <= 1'b0

seems to work fine (i.e., sets the register to all zeros). No
complaints from Altera and the program worked exactly how I wanted (I
have used this type of assignment in other places too).

sharp@cadence.com writes:

It should work fine. It should extend the value with zeroes up to the
desired width. The only reason to use a replication is if you need a
value of an exact width, with no truncation and no extension.

Yes, in simple cases it should work. However, in additon to what
Steve mentioned, there are a few (and very few) weird corner cases in
expressions. If I recall correctly, bit shifts are one example.
Concatenates (and other places where expressions are self-describing)
also need the correct widths. But, if you aren't in one of those
cases, the Verilog extension and truncation rules work quite well.