bit vs std_logic ?

[Squidge]

Can anyone tell me any disadvantages of using 'std_logic' over the builtin
type 'bit'? I'm still learning VHDL, and the books and tutorials I've read
all use 'bit' and 'bit_vector', but I find 'std_logic' and
'std_logic_vector' much more flexible. For example, when creating a
prescaler for an input clock, I normally like to use a simple counter and
assign the clock pin to one of the bits of the counter. I can't work out
how to use a bit_vector as a counter without errors stating that
bit_vector's don't support the '+' operator.

So, can std_logic suitably replace the 'bit' operator, or are there places
where 'bit' would be more suitable ? (flexibility, speed reasons, etc)

 

[jandc]

std_logic models all four states '1', '0', 'X', 'Z' while bit takes
only '0'and '1'.

to be more exact: std_logic models all 9 states: '1', '0', 'X', 'Z',

'U', '-', 'L', 'H', 'W'

 

[Mike Treseler]

Squidge wrote:

Can anyone tell me any disadvantages of using 'std_logic' over the builtin
type 'bit'?

std_logic and std_ulogic are fine for bit types.
However, a counter requires a vector type
with overloads for the '+' operation between
vectors and integers.
Consider using the unsigned type for counters.

http://groups-beta.google.com/groups?q=vhdl+numeric_std+unsigned+std_logic_vector+counter

-- Mike Treseler

 

[Neo]

std_logic models all four states '1', '0', 'X', 'Z' while bit takes
only '0'and '1'.