bit trouble testbenching

[dave]

Hello all,

I'm trying to make a very simple testbench to work with the code on
fpga4fun.com,
when I simulate the clock looks connected by all other signals remain
red on modelsim,

here's the code from fpga4fun

`timescale 1 ns / 100 ps
module hvsync_generator(clk, vga_h_sync, vga_v_sync, inDisplayArea,
CounterX, CounterY);
input clk;
output vga_h_sync, vga_v_sync;
output inDisplayArea;
output [9:0] CounterX;
output [8:0] CounterY;

//////////////////////////////////////////////////
reg [9:0] CounterX;
reg [8:0] CounterY;
wire CounterXmaxed = (CounterX==10'h2FF);

always @(posedge clk)
if(CounterXmaxed)
CounterX <= 0;
else
CounterX <= CounterX + 1;

always @(posedge clk)
if(CounterXmaxed) CounterY <= CounterY + 1;

reg vga_HS, vga_VS;
always @(posedge clk)
begin
vga_HS <= (CounterX[9:4]==6'h2D); // change this value to move the
display horizontally
vga_VS <= (CounterY==500); // change this value to move the display
vertically
end

reg inDisplayArea;
always @(posedge clk)
if(inDisplayArea==0)
inDisplayArea <= (CounterXmaxed) && (CounterY<480);
else
inDisplayArea <= !(CounterX==639);

assign vga_h_sync = ~vga_HS;
assign vga_v_sync = ~vga_VS;

endmodule

and here's my attempt to simulate it:

//---------------------------------------
`timescale 1 ns / 100 ps
module hvsync_generator_tb; // ();
//---------------------------------------
// inputs to the DUT are reg type
reg clk_50;
//reg rst;
//---------------------------------------
// outputs from the DUT are wire type
wire vga_h_sync;
wire vga_v_sync;
wire inDisplayArea;
wire [9:0] CounterX;
wire [8:0] CounterY;
//---------------------------------------
hvsync_generator U1 (
..clk(clk_50),
..vga_h_sync(vga_h_sync),
..vga_v_sync(vga_v_sync),
..inDisplayArea(inDisplayArea),
..CounterX(CounterX),
..CounterY(CounterY)
);
//---------------------------------------
// create a 50Mhz clock
initial begin
clk_50 = 0;
end
always begin
#10 clk_50 = ~clk_50;
end
endmodule
//---------------------------------------

I cant see what is wrong ?

Dave

 

[dave]

Please Ignore
I've added a reset to the module and it works now ,,