Bit-select in named port connection

[Holger Schmidt]

Hi,

I have a module like this:

module a (b[1], b[0]);
output [1:0] b;
reg [1:0] b;
/* some code that sets b */
endmodule

Now I want to instantiate that module. What works is to have an
ordered
list in the module port connection list like this:

wire c, d;
a e(c, d);

Is it possible to change that to a named port connection like this:

a f(.b({c, d}));

The Verilog reference I have says that the name of a port cannot be a
bit-select. Does that mean that I cannot connect by name to something
that is a bit-select in the module definition or does it mean that I
cannot do something like this:

a g(.b[0](d));

Thanks,
Holger

 

[John Penton]

Holger Schmidt wrote:

I have a module like this:

module a (b[1], b[0]);
output [1:0] b;
reg [1:0] b;
/* some code that sets b */
endmodule

Now I want to instantiate that module. What works is to have an
ordered
list in the module port connection list like this:

wire c, d;
a e(c, d);

Is it possible to change that to a named port connection like this:

a f(.b({c, d}));

If you declare your module like:
module a (b);
then this is fine.

The Verilog reference I have says that the name of a port cannot be a
bit-select. Does that mean that I cannot connect by name to something
that is a bit-select in the module definition or does it mean that I
cannot do something like this:

a g(.b[0](d));

I don't believe you can do this.

John

--
John Penton, posting as an individual unless specifically indicated
otherwise.

 

[Ajeetha]

Hi,
V2K LRM clearly states:

-- 12.3.6 Named port instantiation ---------
The port name cannot be a bit-select, a part-select, or a concatenation
of ports.
-----------

Section 12.3.3 makes it even clearer with an example:
---------
module split_ports (a[7:4], a[3:0]); // First port is upper 4 bits of
// 'a'.
// Second port is lower 4 bits of 'a'.
// Can't use named port connections because
// of part-select port 'a'.
-------------------

BTW - I'm curious - how/when do you end up with such names in port
list? After P&R?

Ajeetha
www.noveldv.com

 

[Holger Schmidt]

Ajeetha wrote:

V2K LRM clearly states:

-- 12.3.6 Named port instantiation ---------
The port name cannot be a bit-select, a part-select, or a concatenation
of ports.
-----------

I have 1364-1995 and it says the same in section 12.3.4.

Section 12.3.3 makes it even clearer with an example:
---------
module split_ports (a[7:4], a[3:0]); // First port is upper 4 bits of
// 'a'.
// Second port is lower 4 bits of 'a'.
// Can't use named port connections because
// of part-select port 'a'.
-------------------

Unfortunately that example is not in the 1995 standard. The example
makes it clear.

BTW - I'm curious - how/when do you end up with such names in port
list? After P&R?

Some of the Cadence netlisters from the DFII love to do such things.
However, it's mainly caused by analog designers doing weird things in
the GUI.

Thanks,
Holger

 

[svtechie@gmail.com]

So we can't do it... possible solution can be (if it is intentionally
done by you)

module a (b); // Suggested by Holger
output [1:0] b;
reg [1:0] b;
/* some code that sets b */
endmodule

Instantiation may look like

wire c, d;
a e(.b({c, d}); // Concat to achieve the same
-------------

Thanks
svtechie
www.svtechie.com

 

Some tools will create
module a (\b[0] , \b[1] );
....
And other tools just don't like "\", and remove it or ignore it.
Then you get the funny code style. module a (b[0],b[1]);

Nandy
www.nandigits.com

 

No, you cannot use a named port connection when the module ports are
bit selects instead of identifiers. All port names in named port
connections must be identifiers. Verilog does provide a mechanism for
explicitly declaring an external name for a port, in case the port does
not have a valid external name, or you want an internal port to be
connected to multiple distinct external ports, or you just want the
external name to be different from the internal one. For example:

module a (.g(b[1]), .h(b[0]));
output [1:0] b;

Here the ports are still bit selects of b inside the module, but have
the external names g and h. This then allows you to connect by name,
as in

a f(.g(c), .h(d));

This capability is rarely used. And unfortunately, it doesn't help you
if the module declaration is being created by a tool, since you are
stuck with whatever it produces.