A
Andy Peters
Guest
Here's an odd one. My example is a bit contrived, as I've simplified
it from my real code. Given the following declarations and generate
block:
reg [3:0] ChipSelReg;
wire [3:0] Foo;
generate
genvar i;
for (i = 0; i < 4; i = i + 1) begin : genloop
assign Foo = (ChipSelReg[1:0] == i[1:0]);
end // genloop
endgenerate
Precision Synthesis 2004b.62 accepts this without complaint. The
Altera Quartus 4.2 synthesis tool, however, throws a warning:
"Unconverted VERI-1011: cannot index into non-array i"
According to the Sutherland Verilog-2001 guidebook, genvars are
"special integer variable for use as the index control variable by
generate for loops."
So, even though it has restrictions on its use, a genvar is still an
integer. Therefore, one should expect that it's otherwise a 32 value,
so I should be able to use the bit-select shown above to make it clear
that I wish to compare only the two LSBs for ChipSelReg and the genvar
i. Apparently, Precision agrees with me but Altera doesn't.
Have I stumbled upon Yet Another Verilog Ambiguity?
Thanks,
-a
----------------
Andy Peters
Tucson, AZ
devel at lakte dot net
it from my real code. Given the following declarations and generate
block:
reg [3:0] ChipSelReg;
wire [3:0] Foo;
generate
genvar i;
for (i = 0; i < 4; i = i + 1) begin : genloop
assign Foo = (ChipSelReg[1:0] == i[1:0]);
end // genloop
endgenerate
Precision Synthesis 2004b.62 accepts this without complaint. The
Altera Quartus 4.2 synthesis tool, however, throws a warning:
"Unconverted VERI-1011: cannot index into non-array i"
According to the Sutherland Verilog-2001 guidebook, genvars are
"special integer variable
generate for loops."
So, even though it has restrictions on its use, a genvar is still an
integer. Therefore, one should expect that it's otherwise a 32 value,
so I should be able to use the bit-select shown above to make it clear
that I wish to compare only the two LSBs for ChipSelReg and the genvar
i. Apparently, Precision agrees with me but Altera doesn't.
Have I stumbled upon Yet Another Verilog Ambiguity?
Thanks,
-a
----------------
Andy Peters
Tucson, AZ
devel at lakte dot net