Bit length constraining integers & reals

[Kwaj]

I am trying to analyse the effects of finite word quantisations on the
performance of my VHDL implementation.

A couple of questions

1. what sort of bit length is being employed for real values and integer
values as default? For example

VARIABLE Result: real;

would 'Result' be 16-bit unsigned, 32-bit unsigned or 64-bit unsigned??


2. How would one limit the bit length for the above variable, Result, to
let's say an 8-bit representation??

cheers

- Kingsley

 

[David Bishop]

Kwaj wrote:

I am trying to analyse the effects of finite word quantisations on the
performance of my VHDL implementation.

A couple of questions

1. what sort of bit length is being employed for real values and integer
values as default? For example

VARIABLE Result: real;

would 'Result' be 16-bit unsigned, 32-bit unsigned or 64-bit unsigned??

64 bit floating point. That is the default for the real data type.
Floating point is very different from unsigned.

2. How would one limit the bit length for the above variable, Result, to
let's say an 8-bit representation??

variable result : integer range 0 to 255;
should do it.

--
NAME: David W. Bishop INTERNET: dbishop@vhdl.org