binary to integer conversion code

A

Ashani Patel

Guest
I wrote a simple program to converting 4bit binary to integer and
display the same on my 7 segment leds.
my program got synthesized and mapped and placed and routed . but when
i tried to run this program on my spartan2 kit it shows
different figures on the 7 segment display everytime i give the same
binary number in the input.

it doesnt show correct integer. while when i try to run other programs
they work fine.
 
Ashani Patel wrote:

it doesnt show correct integer. while when i try to run other programs
they work fine.
Click to expand...
I had a similar problem once, a long time ago.

--
Mark McDougall, Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266
 
On Jun 23, 12:10 pm, Mark McDougall <ma...@vl.com.au> wrote:
Ashani Patel wrote:
it doesnt show correct integer. while when i try to run other programs
they work fine.

I had a similar problem once, a long time ago.

--
Mark McDougall, Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266
Click to expand...
HI Mark

what did u do. can u suggest me something
ashani
 
Ashani Patel a écrit :
On Jun 23, 12:10 pm, Mark McDougall <ma...@vl.com.au> wrote:
Ashani Patel wrote:
it doesnt show correct integer. while when i try to run other programs
they work fine.
I had a similar problem once, a long time ago.

--
Mark McDougall, Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266

HI Mark

what did u do. can u suggest me something
ashani
Click to expand...
Start by posting your code

Nicolas
 
On Jun 23, 10:55 am, Nicolas Matringe <nicolas.matri...@fre.fre>
wrote:
Ashani Patel a écrit :



On Jun 23, 12:10 pm, Mark McDougall <ma...@vl.com.au> wrote:
Ashani Patel wrote:
it doesnt show correct integer. while when i try to run other programs
they work fine.
I had a similar problem once, a long time ago.

--
Mark McDougall, Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266

HI Mark

what did u do. can u suggest me something
ashani

Start by posting your code

Nicolas
Click to expand...
here's my code

----------------------------------------------------------------------------------
-- Company:
-- Engineer: Ashani Patel
--
-- Create Date: 20:38:00 05/17/2008
-- Design Name:
-- Module Name: to_integer - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description: converts 4 bit number to integer.
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity to_integer is

generic ( M : integer:= 4 );
Port ( bit_data : in STD_LOGIC_VECTOR (M-1 downto 0);
msb : out std_logic_vector(6 downto 0));

end to_integer;


architecture Behavioral of to_integer is

signal value : integer :=0;
begin

process(bit_data)

variable int_value : integer range 0 to 15:=0; -- i have put this
range for 4 bit
-- otherwise it doesnt get mapped. if i have to make this generic i
cant put this restriction.
-- what is the solution for that.

begin

for N in 0 to M-1 loop
if(bit_data(N) = '1') then
int_value := int_value + 2**N;
end if;
end loop;

value <= int_value;


end process;

process(value)
begin

case value is
when 0 => msb<="1111110";
when 1 => msb<="0011000";
when 2 => msb<="0110111";
when 3 => msb<="0111101";
when 4 => msb<="1011001";
when 5 => msb<="1101101";
when 6 => msb<="1001111";
when 7 => msb<="0111000";
when 8 => msb<="1111111";
when 9 => msb<="1111001";
when others => null;
end case;

end process;
end Behavioral;
 
On Tue, 24 Jun 2008 00:16:54 -0700 (PDT), Ashani Patel
<ashani4001@gmail.com> wrote:

On Jun 23, 10:55 am, Nicolas Matringe <nicolas.matri...@fre.fre
wrote:
Ashani Patel a écrit :



On Jun 23, 12:10 pm, Mark McDougall <ma...@vl.com.au> wrote:
Ashani Patel wrote:
it doesnt show correct integer. while when i try to run other programs
they work fine.

Start by posting your code

process(bit_data)

variable int_value : integer range 0 to 15:=0;
begin

for N in 0 to M-1 loop
if(bit_data(N) = '1') then
int_value := int_value + 2**N;
end if;
end loop;
Click to expand...
Notice that each time the process is triggered, it starts the conversion
from the old value in "int_value", not from zero.

- Brian
 
On Jun 24, 4:31 pm, Brian Drummond <brian_drumm...@btconnect.com>
wrote:
On Tue, 24 Jun 2008 00:16:54 -0700 (PDT), Ashani Patel



ashani4...@gmail.com> wrote:
On Jun 23, 10:55 am, Nicolas Matringe <nicolas.matri...@fre.fre
wrote:
Ashani Patel a écrit :

On Jun 23, 12:10 pm, Mark McDougall <ma...@vl.com.au> wrote:
Ashani Patel wrote:
it doesnt show correct integer. while when i try to run other programs
they work fine.
Start by posting your code
process(bit_data)

variable int_value : integer range 0 to 15:=0;
begin

for N in 0 to M-1 loop
if(bit_data(N) = '1') then
int_value := int_value + 2**N;
end if;
end loop;

Notice that each time the process is triggered, it starts the conversion
from the old value in "int_value", not from zero.

- Brian
Click to expand...
Hi Brian
thanks a lot.
it did work.

regards
ashani
 
If your intention is to convert a 4-bit std_logic_vector to something
that can be shown on a
7 segment display, your solution seems very complicated.

Why not just:

msb <= "1111110" when bit_data = "0000"
else "0011000" when bit_data = "0001"
else ...... .... ........ .......
else ...... .... ........ .......
else "1111111";

/Peter
 
On 25 Juni, 12:21, Peter <peter.hermans...@sts.saab.se> wrote:
  else ......    .... ........ .......
  else "1111111";
Click to expand...
Should have been: else "0000000";

/Peter
 
On Jun 24, 2:16 am, Ashani Patel <ashani4...@gmail.com> wrote:
On Jun 23, 10:55 am, Nicolas Matringe <nicolas.matri...@fre.fre
wrote:



Ashani Patel a écrit :

On Jun 23, 12:10 pm, Mark McDougall <ma...@vl.com.au> wrote:
Ashani Patel wrote:
it doesnt show correct integer. while when i try to run other programs
they work fine.
I had a similar problem once, a long time ago.

--
Mark McDougall, Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266

HI Mark

what did u do. can u suggest me something
ashani

Start by posting your code

Nicolas

here's my code

----------------------------------------------------------------------------------
-- Company:
-- Engineer: Ashani Patel
--
-- Create Date: 20:38:00 05/17/2008
-- Design Name:
-- Module Name: to_integer - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description: converts 4 bit number to integer.
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity to_integer is

generic ( M : integer:= 4 );
Port ( bit_data : in STD_LOGIC_VECTOR (M-1 downto 0);
msb : out std_logic_vector(6 downto 0));

end to_integer;

architecture Behavioral of to_integer is

signal value : integer :=0;
begin

process(bit_data)

variable int_value : integer range 0 to 15:=0; -- i have put this
range for 4 bit
-- otherwise it doesnt get mapped. if i have to make this generic i
cant put this restriction.
-- what is the solution for that.

begin

for N in 0 to M-1 loop
if(bit_data(N) = '1') then
int_value := int_value + 2**N;
end if;
end loop;

value <= int_value;

end process;

process(value)
begin

case value is
when 0 => msb<="1111110";
when 1 => msb<="0011000";
when 2 => msb<="0110111";
when 3 => msb<="0111101";
when 4 => msb<="1011001";
when 5 => msb<="1101101";
when 6 => msb<="1001111";
when 7 => msb<="0111000";
when 8 => msb<="1111111";
when 9 => msb<="1111001";
when others => null;
end case;

end process;
end Behavioral;
Click to expand...
You will get a latch on msb because there are cases where msb is not
assigned. Try when others => msb <= (others => '0');

Also, you can use M to declare the subtype of int_value as 0 to 2**M -
1.


Are you supposed to define your own integer conversion? If not I would
use the numeric_standard package's to_integer() conversion function:

use ieee.numeric_std.all;
...
value <= to_integer(unsigned(bit_data));

Andy
 
On Jun 25, 6:23 pm, Andy <jonesa...@comcast.net> wrote:
On Jun 24, 2:16 am, Ashani Patel <ashani4...@gmail.com> wrote:



On Jun 23, 10:55 am, Nicolas Matringe <nicolas.matri...@fre.fre
wrote:

Ashani Patel a écrit :

On Jun 23, 12:10 pm, Mark McDougall <ma...@vl.com.au> wrote:
Ashani Patel wrote:
it doesnt show correct integer. while when i try to run other programs
they work fine.
I had a similar problem once, a long time ago.

--
Mark McDougall, Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266

HI Mark

what did u do. can u suggest me something
ashani

Start by posting your code

Nicolas

here's my code

----------------------------------------------------------------------------------
-- Company:
-- Engineer: Ashani Patel
--
-- Create Date: 20:38:00 05/17/2008
-- Design Name:
-- Module Name: to_integer - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description: converts 4 bit number to integer.
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity to_integer is

generic ( M : integer:= 4 );
Port ( bit_data : in STD_LOGIC_VECTOR (M-1 downto 0);
msb : out std_logic_vector(6 downto 0));

end to_integer;

architecture Behavioral of to_integer is

signal value : integer :=0;
begin

process(bit_data)

variable int_value : integer range 0 to 15:=0; -- i have put this
range for 4 bit
-- otherwise it doesnt get mapped. if i have to make this generic i
cant put this restriction.
-- what is the solution for that.

begin

for N in 0 to M-1 loop
if(bit_data(N) = '1') then
int_value := int_value + 2**N;
end if;
end loop;

value <= int_value;

end process;

process(value)
begin

case value is
when 0 => msb<="1111110";
when 1 => msb<="0011000";
when 2 => msb<="0110111";
when 3 => msb<="0111101";
when 4 => msb<="1011001";
when 5 => msb<="1101101";
when 6 => msb<="1001111";
when 7 => msb<="0111000";
when 8 => msb<="1111111";
when 9 => msb<="1111001";
when others => null;
end case;

end process;
end Behavioral;

You will get a latch on msb because there are cases where msb is not
assigned. Try when others => msb <= (others => '0');

Also, you can use M to declare the subtype of int_value as 0 to 2**M -
1.

Are you supposed to define your own integer conversion? If not I would
use the numeric_standard package's to_integer() conversion function:

use ieee.numeric_std.all;
...
value <= to_integer(unsigned(bit_data));

Andy
Click to expand...
Hi Peter
thanks but i have made this as generic and was only testing on 4 bit
to see whether i get the output as desired. now i will modify it to
make it generic.
thanks again but solution i can use it in some of my future codes. its
a nice shortcut and very simple and effective.

Hi Andy

i was just writing the code as i have just starting learning vhdl and
wanted to test small programs on my kit before going for big programs.

thanks again for your suggestions too.

the suggestions help a lot

ashani
 
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