Big integer constants

[Hal Murray]

I want to do something like
x <= x + 123456789123123;
where the constant is bigger than 32 bits.

Is there a standard/clean way to do this?

In case it matters, I actually want to pass the constant
in as a generic. I'm willing to write ugly code as long
as it gets good results.

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[Jim Lewis]

I suppose there is the obvious:
split it into more than one integer.

I want to do something like
x <= x + 123456789123123;
where the constant is bigger than 32 bits.

Is there a standard/clean way to do this?

In case it matters, I actually want to pass the constant
in as a generic. I'm willing to write ugly code as long
as it gets good results.

--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training mailto:Jim@SynthWorks.com
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

 

[Mike Treseler]

Hal Murray wrote:

I want to do something like
x <= x + 123456789123123;
where the constant is bigger than 32 bits.

Is there a standard/clean way to do this?

Type unsigned can handle it.

-- Mike Treseler

 

hmurray@suespammers.org (Hal Murray) writes:

I want to do something like
x <= x + 123456789123123;
where the constant is bigger than 32 bits.

Is there a standard/clean way to do this?

Use hex or aggregates:

unsigned(to_stdlogicvector(bit_vector'(X"00007048860F9033"))(63 DOWNTO 0))

or

(46 DOWNTO 44 => '1',
38 => '1', 35 => '1', 31 => '1',
26 DOWNTO 25 => '1',
19 DOWNTO 15 => '1',
12 => '1',
5 DOWNTO 4 => '1',
1 DOWNTO 0 => '1',
OTHERS => '0')

 

[Paul Uiterlinden]

bko-no-spam-please@ieee.org wrote:

hmurray@suespammers.org (Hal Murray) writes:


I want to do something like
x <= x + 123456789123123;
where the constant is bigger than 32 bits.

Is there a standard/clean way to do this?


Use hex or aggregates:

unsigned(to_stdlogicvector(bit_vector'(X"00007048860F9033"))(63 DOWNTO 0))

The qualification and conversions are not needed. Since the 93 standard
bit literals may be used for std_logic_vectors (and signed/unsigned) as
well. So the following is valid:

example: PROCESS IS
VARIABLE uns: unsigned(63 DOWNTO 0);
BEGIN
uns := uns + X"1234567890ABCDEF";
WAIT;
END PROCESS example;

Paul.

 

Paul Uiterlinden <no@spam.nl> writes:

bko-no-spam-please@ieee.org wrote:
hmurray@suespammers.org (Hal Murray) writes:

I want to do something like
x <= x + 123456789123123;
where the constant is bigger than 32 bits.

Is there a standard/clean way to do this?
Use hex or aggregates:
unsigned(to_stdlogicvector(bit_vector'(X"00007048860F9033"))(63 DOWNTO 0))

The qualification and conversions are not needed. Since the 93 standard bit
literals may be used for std_logic_vectors (and signed/unsigned) as well. So the
following is valid:

example: PROCESS IS
VARIABLE uns: unsigned(63 DOWNTO 0);
BEGIN
uns := uns + X"1234567890ABCDEF";
WAIT;
END PROCESS example;

Yes, I have should have been clearer in saying that all the extra conversions
etc. are only needed if you want the expression to work in both the -87 and -93
environments. This is the standard idiom that is in the VHDL FAQ for such dual
environment use.

By way of defense I can say that at least one major simulator only recently
(June 2004) changed their default to be VHDL-93 instead of -87.