Bidirectional Port Problem

D

Debjit

Guest
Hi All,

I am facing a peculiar problem.
I have installed Cadence ICFB version 5.10.41_USR6.127.29 and Cadence
IUS58 in two servers. In one of the Server, during spectreVerilog
simulation , the simulator does not complain about the bidirectional
ports and simulates perfectly. But the same circuit, when simulated in
other server, the simulator complains about the bidirectional ports
present in the circuit. Even if I remove those bidirectional ports
with input ports, but it fails to simulate.
The problem appears very ridiculous at first glance but I am facing
this problem for the past 3 days. Can any one please suggest the
possible causes for this anomaly?
Thanks in advance for your help.


------------------------------

Thanking you,

Yours sincerely,
Debjit
======================
Debjit Pal
MS Student and Research Consultant
Department of Computer Science and Engineering
IIT Kharagpur
Mobile: +91-9432873973
 
Debjit wrote, on 09/04/09 06:17:
Hi All,

I am facing a peculiar problem.
I have installed Cadence ICFB version 5.10.41_USR6.127.29 and Cadence
IUS58 in two servers. In one of the Server, during spectreVerilog
simulation , the simulator does not complain about the bidirectional
ports and simulates perfectly. But the same circuit, when simulated in
other server, the simulator complains about the bidirectional ports
present in the circuit. Even if I remove those bidirectional ports
with input ports, but it fails to simulate.
The problem appears very ridiculous at first glance but I am facing
this problem for the past 3 days. Can any one please suggest the
possible causes for this anomaly?
Thanks in advance for your help.


------------------------------

Thanking you,

Yours sincerely,
Debjit
======================
Debjit Pal
MS Student and Research Consultant
Department of Computer Science and Engineering
IIT Kharagpur
Mobile: +91-9432873973
Click to expand...
Well, bidirectional ports (at the analog/digital interface) are not supported in
spectreVerilog (you'd have to use AMS Designer for that), so that would explain
why it complains. But why it is different on different servers? Well, clearly
_something_ must be different.

I'd suggest comparing the netlists between the two runs to see if there are any
differences (use diff?)

I've not heard of such a scenario. Perhaps the data being accessed is actually
different on the two servers? Comparing the netlists should show that though.

Regards,

Andrew.
 
On Sep 4, 3:48 pm, Andrew Beckett <andr...@DcEaLdEeTnEcTe.HcIoSm>
wrote:
Debjit wrote, on 09/04/09 06:17:



Hi All,

I am facing a peculiar problem.
I have installed Cadence ICFB version 5.10.41_USR6.127.29 and Cadence
IUS58 in two servers. In one of the Server, during spectreVerilog
simulation , the simulator does not complain about the bidirectional
ports and simulates perfectly. But the same circuit, when simulated in
other server, the simulator complains about the bidirectional ports
present in the circuit. Even if I remove those bidirectional ports
with input ports, but it fails to simulate.
The problem appears very ridiculous at first glance but I am facing
this problem for the past 3 days. Can any one please suggest the
possible causes for this anomaly?
Thanks in advance for your help.

------------------------------

Thanking you,

Yours sincerely,
Debjit
=====================> > Debjit Pal
MS Student and Research Consultant
Department of Computer Science and Engineering
IIT Kharagpur
Mobile: +91-9432873973

Well, bidirectional ports (at the analog/digital interface) are not supported in
spectreVerilog (you'd have to use AMS Designer for that), so that would explain
why it complains. But why it is different on different servers? Well, clearly
_something_ must be different.

I'd suggest comparing the netlists between the two runs to see if there are any
differences (use diff?)

I've not heard of such a scenario. Perhaps the data being accessed is actually
different on the two servers? Comparing the netlists should show that though.

Regards,

Andrew.
Click to expand...
Hi Andrew,

I do not know what is really going on. But thats the problem I am
facing when I am going to simulate the same circuit with same library.
The only difference is in the version of the Cadence ICFB and RHEL.
One of them using RHEL5 and another using RHEL4. I am really puzzuled
about the fact.
After a few days trial and error, finally I got a the message in the
spectre.out file which I am just copying in this mail. I think the
bidirectional port problem is gone but a new problem has arived.


\i load "/research2/antara/Final_Tool_Jun_09/
Integrated_Template_Tool_V2_Demo/test_cadence_vlsi/createViews.il"
\w *WARNING* The directory: '/designPackages/design_installer/cmos7_5v/
R10.4/libraries/std_cells/c7lite5vhdlui_co/opus_50/c7lite5vhdlui_co'
does not exist
\w but was defined in libFile '/designPackages/design_installer/
cmos7_5v/R10.4/tools/ace/public/cmos7_5v_50/release/cmos7_5v/setup/
libraryPath/rev.20070306_1712/cds.lib' for Lib 'c7lite5vhdlui_co'.
\w *WARNING* The directory: '/designPackages/design_installer/cmos7_5v/
R10.4/libraries/std_cells/c7lite5vhdlui_co/opus_50/c7lite5vhdlui_co'
does not exist
\w but was defined in libFile '/designPackages/design_installer/
cmos7_5v/R10.4/tools/ace/public/cmos7_5v_50/release/cmos7_5v/setup/
libraryPath/rev.20070306_1712/cds.lib' for Lib 'c7lite5vhdlui_co'.
\o Loading ahdlSck.cxt
\o Loading schHDL.cxt
\o veriloga Diagnostics: Warnings exist in veriloga text of cell
state_ldo_ldod001_c2.
\o
\o Warning from spectre during SpectreHDL compile.
\o "/research2/antara/ICFB/lp3919_c3_10R2/state_ldo_ldod001_c2/
veriloga/veriloga.va",
\o line 98: Warning: `(abs)delay()' does not account for phase
shift in
\o small-signal analysis.
\o "/research2/antara/ICFB/lp3919_c3_10R2/state_ldo_ldod001_c2/
veriloga/veriloga.va",
\o line 99: Warning: `(abs)delay()' does not account for phase
shift in
\o small-signal analysis.
\o "/research2/antara/ICFB/lp3919_c3_10R2/state_ldo_ldod001_c2/
veriloga/veriloga.va",
\o line 100: Warning: `(abs)delay()' does not account for
phase shift in
\o small-signal analysis.
\o Compiling ahdlcmi module library.
\o Failed to compile ahdlcmi module library, see
\o /research2/antara/ICFB/lp3919_c3_10R2/state_ldo_ldod001_c2/
veriloga/veriloga.va.ahdlcmi/
\o for details
\o Could not open ahdlcmi module library
\o /research2/antara/ICFB/lp3919_c3_10R2/state_ldo_ldod001_c2/
veriloga/veriloga.va.ahdlcmi/obj/Linux2.6.18-92.el5PAE+gcc/optimize/
libahdlcmi.so
\o /research2/antara/ICFB/lp3919_c3_10R2/state_ldo_ldod001_c2/
veriloga/veriloga.va.ahdlcmi/obj/Linux2.6.18-92.el5PAE+gcc/optimize/
libahdlcmi.so:
\o cannot open shared object file: No such file or directory
\o Symbol (state_ldo_ldod001_c2 symbol) generated and saved in
library:lp3919_c3_10R2.
\o Completed generating design in library "lp3919_c3_10R2" as
"state_ldo_ldod001_c2" "symbol".
\w *WARNING* The directory: '/designPackages/design_installer/cmos7_5v/
R10.4/libraries/std_cells/c7lite5vhdlui_co/opus_50/c7lite5vhdlui_co'
does not exist
\w but was defined in libFile '/designPackages/design_installer/
cmos7_5v/R10.4/tools/ace/public/cmos7_5v_50/release/cmos7_5v/setup/
libraryPath/rev.20070306_1712/cds.lib' for Lib 'c7lite5vhdlui_co'.
\w *WARNING* The directory: '/designPackages/design_installer/cmos7_5v/
R10.4/libraries/std_cells/c7lite5vhdlui_co/opus_50/c7lite5vhdlui_co'
does not exist
\w but was defined in libFile '/designPackages/design_installer/
cmos7_5v/R10.4/tools/ace/public/cmos7_5v_50/release/cmos7_5v/setup/
libraryPath/rev.20070306_1712/cds.lib' for Lib 'c7lite5vhdlui_co'.
\o veriloga Diagnostics: Warnings exist in veriloga text of cell
analog_mux_LDO.
\o Compiling ahdlcmi module library.
\o Failed to compile ahdlcmi module library, see
\o /research2/antara/ICFB/lp3919_c3_10R2/analog_mux_LDO/
veriloga/veriloga.va.ahdlcmi/
\o for details
\o Could not open ahdlcmi module library
\o /research2/antara/ICFB/lp3919_c3_10R2/analog_mux_LDO/
veriloga/veriloga.va.ahdlcmi/obj/Linux2.6.18-92.el5PAE+gcc/optimize/
libahdlcmi.so
\o /research2/antara/ICFB/lp3919_c3_10R2/analog_mux_LDO/
veriloga/veriloga.va.ahdlcmi/obj/Linux2.6.18-92.el5PAE+gcc/optimize/
libahdlcmi.so:
\o cannot open shared object file: No such file or directory
\o Symbol (analog_mux_LDO symbol) generated and saved in
library:lp3919_c3_10R2.
\o Completed generating design in library "lp3919_c3_10R2" as
"analog_mux_LDO" "symbol".
\w *WARNING* The directory: '/designPackages/design_installer/cmos7_5v/
R10.4/libraries/std_cells/c7lite5vhdlui_co/opus_50/c7lite5vhdlui_co'
does not exist
\w but was defined in libFile '/designPackages/design_installer/
cmos7_5v/R10.4/tools/ace/public/cmos7_5v_50/release/cmos7_5v/setup/
libraryPath/rev.20070306_1712/cds.lib' for Lib 'c7lite5vhdlui_co'.
\w *WARNING* The directory: '/designPackages/design_installer/cmos7_5v/
R10.4/libraries/std_cells/c7lite5vhdlui_co/opus_50/c7lite5vhdlui_co'
does not exist
\w but was defined in libFile '/designPackages/design_installer/
cmos7_5v/R10.4/tools/ace/public/cmos7_5v_50/release/cmos7_5v/setup/
libraryPath/rev.20070306_1712/cds.lib' for Lib 'c7lite5vhdlui_co'.
\o veriloga Diagnostics: Warnings exist in veriloga text of cell
ideal_switch.
\o Compiling ahdlcmi module library.
\o Failed to compile ahdlcmi module library, see
\o /research2/antara/ICFB/lp3919_c3_10R2/ideal_switch/veriloga/
veriloga.va.ahdlcmi/
\o for details
\o Could not open ahdlcmi module library
\o /research2/antara/ICFB/lp3919_c3_10R2/ideal_switch/veriloga/
veriloga.va.ahdlcmi/obj/Linux2.6.18-92.el5PAE+gcc/optimize/
libahdlcmi.so
\o /research2/antara/ICFB/lp3919_c3_10R2/ideal_switch/veriloga/
veriloga.va.ahdlcmi/obj/Linux2.6.18-92.el5PAE+gcc/optimize/
libahdlcmi.so:
\o cannot open shared object file: No such file or directory
\o Symbol (ideal_switch symbol) generated and saved in
library:lp3919_c3_10R2.
\o Completed generating design in library "lp3919_c3_10R2" as
"ideal_switch" "symbol".
\w *WARNING* The directory: '/designPackages/design_installer/cmos7_5v/
R10.4/libraries/std_cells/c7lite5vhdlui_co/opus_50/c7lite5vhdlui_co'
does not exist
\w but was defined in libFile '/designPackages/design_installer/
cmos7_5v/R10.4/tools/ace/public/cmos7_5v_50/release/cmos7_5v/setup/
libraryPath/rev.20070306_1712/cds.lib' for Lib 'c7lite5vhdlui_co'.
\w *WARNING* The directory: '/designPackages/design_installer/cmos7_5v/
R10.4/libraries/std_cells/c7lite5vhdlui_co/opus_50/c7lite5vhdlui_co'
does not exist
\w but was defined in libFile '/designPackages/design_installer/
cmos7_5v/R10.4/tools/ace/public/cmos7_5v_50/release/cmos7_5v/setup/
libraryPath/rev.20070306_1712/cds.lib' for Lib 'c7lite5vhdlui_co'.
\o veriloga Diagnostics: Successful syntax check for veriloga text of
cell Shutdown.
\o Symbol (Shutdown symbol) generated and saved in
library:lp3919_c3_10R2.
\o Completed generating design in library "lp3919_c3_10R2" as
"Shutdown" "symbol".
\w *WARNING* The directory: '/designPackages/design_installer/cmos7_5v/
R10.4/libraries/std_cells/c7lite5vhdlui_co/opus_50/c7lite5vhdlui_co'
does not exist
\w but was defined in libFile '/designPackages/design_installer/
cmos7_5v/R10.4/tools/ace/public/cmos7_5v_50/release/cmos7_5v/setup/
libraryPath/rev.20070306_1712/cds.lib' for Lib 'c7lite5vhdlui_co'.
\w *WARNING* The directory: '/designPackages/design_installer/cmos7_5v/
R10.4/libraries/std_cells/c7lite5vhdlui_co/opus_50/c7lite5vhdlui_co'
does not exist
\w but was defined in libFile '/designPackages/design_installer/
cmos7_5v/R10.4/tools/ace/public/cmos7_5v_50/release/cmos7_5v/setup/
libraryPath/rev.20070306_1712/cds.lib' for Lib 'c7lite5vhdlui_co'.
\o veriloga Diagnostics: Warnings exist in veriloga text of cell
cccs2.
\o Compiling ahdlcmi module library.
\o Failed to compile ahdlcmi module library, see
\o /research2/antara/ICFB/lp3919_c3_10R2/cccs2/veriloga/
veriloga.va.ahdlcmi/
\o for details
\o Could not open ahdlcmi module library
\o /research2/antara/ICFB/lp3919_c3_10R2/cccs2/veriloga/
veriloga.va.ahdlcmi/obj/Linux2.6.18-92.el5PAE+gcc/optimize/
libahdlcmi.so
\o /research2/antara/ICFB/lp3919_c3_10R2/cccs2/veriloga/
veriloga.va.ahdlcmi/obj/Linux2.6.18-92.el5PAE+gcc/optimize/
libahdlcmi.so:
\o cannot open shared object file: No such file or directory
\o Symbol (cccs2 symbol) generated and saved in
library:lp3919_c3_10R2.
\o Completed generating design in library "lp3919_c3_10R2" as "cccs2"
"symbol".
\w *WARNING* The directory: '/designPackages/design_installer/cmos7_5v/
R10.4/libraries/std_cells/c7lite5vhdlui_co/opus_50/c7lite5vhdlui_co'
does not exist
\w but was defined in libFile '/designPackages/design_installer/
cmos7_5v/R10.4/tools/ace/public/cmos7_5v_50/release/cmos7_5v/setup/
libraryPath/rev.20070306_1712/cds.lib' for Lib 'c7lite5vhdlui_co'.
\w *WARNING* The directory: '/designPackages/design_installer/cmos7_5v/
R10.4/libraries/std_cells/c7lite5vhdlui_co/opus_50/c7lite5vhdlui_co'
does not exist
\w but was defined in libFile '/designPackages/design_installer/
cmos7_5v/R10.4/tools/ace/public/cmos7_5v_50/release/cmos7_5v/setup/
libraryPath/rev.20070306_1712/cds.lib' for Lib 'c7lite5vhdlui_co'.
\o veriloga Diagnostics: Successful syntax check for veriloga text of
cell startup1.
\o Symbol (startup1 symbol) generated and saved in
library:lp3919_c3_10R2.
\o Completed generating design in library "lp3919_c3_10R2" as
"startup1" "symbol".
\w *WARNING* The directory: '/designPackages/design_installer/cmos7_5v/
R10.4/libraries/std_cells/c7lite5vhdlui_co/opus_50/c7lite5vhdlui_co'
does not exist
\w but was defined in libFile '/designPackages/design_installer/
cmos7_5v/R10.4/tools/ace/public/cmos7_5v_50/release/cmos7_5v/setup/
libraryPath/rev.20070306_1712/cds.lib' for Lib 'c7lite5vhdlui_co'.
\w *WARNING* The directory: '/designPackages/design_installer/cmos7_5v/
R10.4/libraries/std_cells/c7lite5vhdlui_co/opus_50/c7lite5vhdlui_co'
does not exist
\w but was defined in libFile '/designPackages/design_installer/
cmos7_5v/R10.4/tools/ace/public/cmos7_5v_50/release/cmos7_5v/setup/
libraryPath/rev.20070306_1712/cds.lib' for Lib 'c7lite5vhdlui_co'.
\o veriloga Diagnostics: Warnings exist in veriloga text of cell
steady_out.
\o Compiling ahdlcmi module library.
\o Failed to compile ahdlcmi module library, see
\o /research2/antara/ICFB/lp3919_c3_10R2/steady_out/veriloga/
veriloga.va.ahdlcmi/
\o for details
\o Could not open ahdlcmi module library
\o /research2/antara/ICFB/lp3919_c3_10R2/steady_out/veriloga/
veriloga.va.ahdlcmi/obj/Linux2.6.18-92.el5PAE+gcc/optimize/
libahdlcmi.so
\o /research2/antara/ICFB/lp3919_c3_10R2/steady_out/veriloga/
veriloga.va.ahdlcmi/obj/Linux2.6.18-92.el5PAE+gcc/optimize/
libahdlcmi.so:
\o cannot open shared object file: No such file or directory
\o Symbol (steady_out symbol) generated and saved in
library:lp3919_c3_10R2.
\o Completed generating design in library "lp3919_c3_10R2" as
"steady_out" "symbol".
\w *WARNING* The directory: '/designPackages/design_installer/cmos7_5v/
R10.4/libraries/std_cells/c7lite5vhdlui_co/opus_50/c7lite5vhdlui_co'
does not exist
\w but was defined in libFile '/designPackages/design_installer/
cmos7_5v/R10.4/tools/ace/public/cmos7_5v_50/release/cmos7_5v/setup/
libraryPath/rev.20070306_1712/cds.lib' for Lib 'c7lite5vhdlui_co'.
\w *WARNING* The directory: '/designPackages/design_installer/cmos7_5v/
R10.4/libraries/std_cells/c7lite5vhdlui_co/opus_50/c7lite5vhdlui_co'
does not exist
\w but was defined in libFile '/designPackages/design_installer/
cmos7_5v/R10.4/tools/ace/public/cmos7_5v_50/release/cmos7_5v/setup/
libraryPath/rev.20070306_1712/cds.lib' for Lib 'c7lite5vhdlui_co'.
\o veriloga Diagnostics: Warnings exist in veriloga text of cell
clocked_cccs.
\o
\o Warning from spectre during SpectreHDL compile.
\o "/research2/antara/ICFB/lp3919_c3_10R2/clocked_cccs/veriloga/
veriloga.va",
\o line 18: Warning: (Archaic Syntax) Does not comply with the
Accellera
\o Verilog-AMS 2.0 Standard and beyond. To comply with the
current
\o standard, assign a value to `loadcurrent'. A variable that
is never
\o assigned a value is considered a digital variable in
Verilog-AMS and is
\o therefore not pure Verilog-A.
\o Compiling ahdlcmi module library.
\o Failed to compile ahdlcmi module library, see
\o /research2/antara/ICFB/lp3919_c3_10R2/clocked_cccs/veriloga/
veriloga.va.ahdlcmi/
\o for details
\o Could not open ahdlcmi module library
\o /research2/antara/ICFB/lp3919_c3_10R2/clocked_cccs/veriloga/
veriloga.va.ahdlcmi/obj/Linux2.6.18-92.el5PAE+gcc/optimize/
libahdlcmi.so
\o /research2/antara/ICFB/lp3919_c3_10R2/clocked_cccs/veriloga/
veriloga.va.ahdlcmi/obj/Linux2.6.18-92.el5PAE+gcc/optimize/
libahdlcmi.so:
\o cannot open shared object file: No such file or directory
\o Symbol (clocked_cccs symbol) generated and saved in
library:lp3919_c3_10R2.
\o Completed generating design in library "lp3919_c3_10R2" as
"clocked_cccs" "symbol".
\w *WARNING* The directory: '/designPackages/design_installer/cmos7_5v/
R10.4/libraries/std_cells/c7lite5vhdlui_co/opus_50/c7lite5vhdlui_co'
does not exist
\w but was defined in libFile '/designPackages/design_installer/
cmos7_5v/R10.4/tools/ace/public/cmos7_5v_50/release/cmos7_5v/setup/
libraryPath/rev.20070306_1712/cds.lib' for Lib 'c7lite5vhdlui_co'.
\w *WARNING* The directory: '/designPackages/design_installer/cmos7_5v/
R10.4/libraries/std_cells/c7lite5vhdlui_co/opus_50/c7lite5vhdlui_co'
does not exist
\w but was defined in libFile '/designPackages/design_installer/
cmos7_5v/R10.4/tools/ace/public/cmos7_5v_50/release/cmos7_5v/setup/
libraryPath/rev.20070306_1712/cds.lib' for Lib 'c7lite5vhdlui_co'.
\o veriloga Diagnostics: Warnings exist in veriloga text of cell
outputvoltage_sense.
\o Compiling ahdlcmi module library.
\o Failed to compile ahdlcmi module library, see
\o /research2/antara/ICFB/lp3919_c3_10R2/outputvoltage_sense/
veriloga/veriloga.va.ahdlcmi/
\o for details
\o Could not open ahdlcmi module library
\o /research2/antara/ICFB/lp3919_c3_10R2/outputvoltage_sense/
veriloga/veriloga.va.ahdlcmi/obj/Linux2.6.18-92.el5PAE+gcc/optimize/
libahdlcmi.so
\o /research2/antara/ICFB/lp3919_c3_10R2/outputvoltage_sense/
veriloga/veriloga.va.ahdlcmi/obj/Linux2.6.18-92.el5PAE+gcc/optimize/
libahdlcmi.so:
\o cannot open shared object file: No such file or directory
\o Symbol (outputvoltage_sense symbol) generated and saved in
library:lp3919_c3_10R2.
\o Completed generating design in library "lp3919_c3_10R2" as
"outputvoltage_sense" "symbol".
\w *WARNING* The directory: '/designPackages/design_installer/cmos7_5v/
R10.4/libraries/std_cells/c7lite5vhdlui_co/opus_50/c7lite5vhdlui_co'
does not exist
\w but was defined in libFile '/designPackages/design_installer/
cmos7_5v/R10.4/tools/ace/public/cmos7_5v_50/release/cmos7_5v/setup/
libraryPath/rev.20070306_1712/cds.lib' for Lib 'c7lite5vhdlui_co'.
\w *WARNING* The directory: '/designPackages/design_installer/cmos7_5v/
R10.4/libraries/std_cells/c7lite5vhdlui_co/opus_50/c7lite5vhdlui_co'
does not exist
\w but was defined in libFile '/designPackages/design_installer/
cmos7_5v/R10.4/tools/ace/public/cmos7_5v_50/release/cmos7_5v/setup/
libraryPath/rev.20070306_1712/cds.lib' for Lib 'c7lite5vhdlui_co'.
\o veriloga Diagnostics: Warnings exist in veriloga text of cell
startup_control.
\o Compiling ahdlcmi module library.
\o Failed to compile ahdlcmi module library, see
\o /research2/antara/ICFB/lp3919_c3_10R2/startup_control/
veriloga/veriloga.va.ahdlcmi/
\o for details
\o Could not open ahdlcmi module library
\o /research2/antara/ICFB/lp3919_c3_10R2/startup_control/
veriloga/veriloga.va.ahdlcmi/obj/Linux2.6.18-92.el5PAE+gcc/optimize/
libahdlcmi.so
\o /research2/antara/ICFB/lp3919_c3_10R2/startup_control/
veriloga/veriloga.va.ahdlcmi/obj/Linux2.6.18-92.el5PAE+gcc/optimize/
libahdlcmi.so:
\o cannot open shared object file: No such file or directory
\o Symbol (startup_control symbol) generated and saved in
library:lp3919_c3_10R2.
\o Completed generating design in library "lp3919_c3_10R2" as
"startup_control" "symbol".
\w *WARNING* The directory: '/designPackages/design_installer/cmos7_5v/
R10.4/libraries/std_cells/c7lite5vhdlui_co/opus_50/c7lite5vhdlui_co'
does not exist
\w but was defined in libFile '/designPackages/design_installer/
cmos7_5v/R10.4/tools/ace/public/cmos7_5v_50/release/cmos7_5v/setup/
libraryPath/rev.20070306_1712/cds.lib' for Lib 'c7lite5vhdlui_co'.
\w *WARNING* The directory: '/designPackages/design_installer/cmos7_5v/
R10.4/libraries/std_cells/c7lite5vhdlui_co/opus_50/c7lite5vhdlui_co'
does not exist
\w but was defined in libFile '/designPackages/design_installer/
cmos7_5v/R10.4/tools/ace/public/cmos7_5v_50/release/cmos7_5v/setup/
libraryPath/rev.20070306_1712/cds.lib' for Lib 'c7lite5vhdlui_co'.
\o veriloga Diagnostics: Warnings exist in veriloga text of cell
vout_and_trim_block_ldod001_c2.
\o Compiling ahdlcmi module library.
\o Failed to compile ahdlcmi module library, see
\o /research2/antara/ICFB/lp3919_c3_10R2/
vout_and_trim_block_ldod001_c2/veriloga/veriloga.va.ahdlcmi/
\o for details
\o Could not open ahdlcmi module library
\o /research2/antara/ICFB/lp3919_c3_10R2/
vout_and_trim_block_ldod001_c2/veriloga/veriloga.va.ahdlcmi/obj/
Linux2.6.18-92.el5PAE+gcc/optimize/libahdlcmi.so
\o /research2/antara/ICFB/lp3919_c3_10R2/
vout_and_trim_block_ldod001_c2/veriloga/veriloga.va.ahdlcmi/obj/
Linux2.6.18-92.el5PAE+gcc/optimize/libahdlcmi.so:
\o cannot open shared object file: No such file or directory
\o Symbol (vout_and_trim_block_ldod001_c2 symbol) generated and saved
in library:lp3919_c3_10R2.
\o Completed generating design in library "lp3919_c3_10R2" as
"vout_and_trim_block_ldod001_c2" "symbol".
\w *WARNING* The directory: '/designPackages/design_installer/cmos7_5v/
R10.4/libraries/std_cells/c7lite5vhdlui_co/opus_50/c7lite5vhdlui_co'
does not exist
\w but was defined in libFile '/designPackages/design_installer/
cmos7_5v/R10.4/tools/ace/public/cmos7_5v_50/release/cmos7_5v/setup/
libraryPath/rev.20070306_1712/cds.lib' for Lib 'c7lite5vhdlui_co'.
\w *WARNING* The directory: '/designPackages/design_installer/cmos7_5v/
R10.4/libraries/std_cells/c7lite5vhdlui_co/opus_50/c7lite5vhdlui_co'
does not exist
\w but was defined in libFile '/designPackages/design_installer/
cmos7_5v/R10.4/tools/ace/public/cmos7_5v_50/release/cmos7_5v/setup/
libraryPath/rev.20070306_1712/cds.lib' for Lib 'c7lite5vhdlui_co'.
\o veriloga Diagnostics: Warnings exist in veriloga text of cell
current_limit.
\o Compiling ahdlcmi module library.
\o Failed to compile ahdlcmi module library, see
\o /research2/antara/ICFB/lp3919_c3_10R2/current_limit/
veriloga/veriloga.va.ahdlcmi/
\o for details
\o Could not open ahdlcmi module library
\o /research2/antara/ICFB/lp3919_c3_10R2/current_limit/
veriloga/veriloga.va.ahdlcmi/obj/Linux2.6.18-92.el5PAE+gcc/optimize/
libahdlcmi.so
\o /research2/antara/ICFB/lp3919_c3_10R2/current_limit/
veriloga/veriloga.va.ahdlcmi/obj/Linux2.6.18-92.el5PAE+gcc/optimize/
libahdlcmi.so:
\o cannot open shared object file: No such file or directory
\o Symbol (current_limit symbol) generated and saved in
library:lp3919_c3_10R2.
\o Completed generating design in library "lp3919_c3_10R2" as
"current_limit" "symbol".
\w *WARNING* The directory: '/designPackages/design_installer/cmos7_5v/
R10.4/libraries/std_cells/c7lite5vhdlui_co/opus_50/c7lite5vhdlui_co'
does not exist
\w but was defined in libFile '/designPackages/design_installer/
cmos7_5v/R10.4/tools/ace/public/cmos7_5v_50/release/cmos7_5v/setup/
libraryPath/rev.20070306_1712/cds.lib' for Lib 'c7lite5vhdlui_co'.
\w *WARNING* The directory: '/designPackages/design_installer/cmos7_5v/
R10.4/libraries/std_cells/c7lite5vhdlui_co/opus_50/c7lite5vhdlui_co'
does not exist
\w but was defined in libFile '/designPackages/design_installer/
cmos7_5v/R10.4/tools/ace/public/cmos7_5v_50/release/cmos7_5v/setup/
libraryPath/rev.20070306_1712/cds.lib' for Lib 'c7lite5vhdlui_co'.
\o veriloga Diagnostics: Warnings exist in veriloga text of cell
sensor1.
\o Compiling ahdlcmi module library.
\o Failed to compile ahdlcmi module library, see
\o /research2/antara/ICFB/lp3919_c3_10R2/sensor1/veriloga/
veriloga.va.ahdlcmi/
\o for details
\o Could not open ahdlcmi module library
\o /research2/antara/ICFB/lp3919_c3_10R2/sensor1/veriloga/
veriloga.va.ahdlcmi/obj/Linux2.6.18-92.el5PAE+gcc/optimize/
libahdlcmi.so
\o /research2/antara/ICFB/lp3919_c3_10R2/sensor1/veriloga/
veriloga.va.ahdlcmi/obj/Linux2.6.18-92.el5PAE+gcc/optimize/
libahdlcmi.so:
\o cannot open shared object file: No such file or directory
\o Symbol (sensor1 symbol) generated and saved in
library:lp3919_c3_10R2.
\o Completed generating design in library "lp3919_c3_10R2" as
"sensor1" "symbol".
\w *WARNING* The directory: '/designPackages/design_installer/cmos7_5v/
R10.4/libraries/std_cells/c7lite5vhdlui_co/opus_50/c7lite5vhdlui_co'
does not exist
\w but was defined in libFile '/designPackages/design_installer/
cmos7_5v/R10.4/tools/ace/public/cmos7_5v_50/release/cmos7_5v/setup/
libraryPath/rev.20070306_1712/cds.lib' for Lib 'c7lite5vhdlui_co'.
\w *WARNING* The directory: '/designPackages/design_installer/cmos7_5v/
R10.4/libraries/std_cells/c7lite5vhdlui_co/opus_50/c7lite5vhdlui_co'
does not exist
\w but was defined in libFile '/designPackages/design_installer/
cmos7_5v/R10.4/tools/ace/public/cmos7_5v_50/release/cmos7_5v/setup/
libraryPath/rev.20070306_1712/cds.lib' for Lib 'c7lite5vhdlui_co'.
\o veriloga Diagnostics: Warnings exist in veriloga text of cell
startup_opstage1.
\o
\o Warning from spectre during SpectreHDL compile.
\o "/research2/antara/ICFB/lp3919_c3_10R2/startup_opstage1/
veriloga/veriloga.va",
\o line 37: Warning: `(abs)delay()' does not account for phase
shift in
\o small-signal analysis.
\o Compiling ahdlcmi module library.
\o Failed to compile ahdlcmi module library, see
\o /research2/antara/ICFB/lp3919_c3_10R2/startup_opstage1/
veriloga/veriloga.va.ahdlcmi/
\o for details
\o Could not open ahdlcmi module library
\o /research2/antara/ICFB/lp3919_c3_10R2/startup_opstage1/
veriloga/veriloga.va.ahdlcmi/obj/Linux2.6.18-92.el5PAE+gcc/optimize/
libahdlcmi.so
\o /research2/antara/ICFB/lp3919_c3_10R2/startup_opstage1/
veriloga/veriloga.va.ahdlcmi/obj/Linux2.6.18-92.el5PAE+gcc/optimize/
libahdlcmi.so:
\o cannot open shared object file: No such file or directory
\o Symbol (startup_opstage1 symbol) generated and saved in
library:lp3919_c3_10R2.
\o Completed generating design in library "lp3919_c3_10R2" as
"startup_opstage1" "symbol".
\w *WARNING* The directory: '/designPackages/design_installer/cmos7_5v/
R10.4/libraries/std_cells/c7lite5vhdlui_co/opus_50/c7lite5vhdlui_co'
does not exist
\w but was defined in libFile '/designPackages/design_installer/
cmos7_5v/R10.4/tools/ace/public/cmos7_5v_50/release/cmos7_5v/setup/
libraryPath/rev.20070306_1712/cds.lib' for Lib 'c7lite5vhdlui_co'.
\w *WARNING* The directory: '/designPackages/design_installer/cmos7_5v/
R10.4/libraries/std_cells/c7lite5vhdlui_co/opus_50/c7lite5vhdlui_co'
does not exist
\w but was defined in libFile '/designPackages/design_installer/
cmos7_5v/R10.4/tools/ace/public/cmos7_5v_50/release/cmos7_5v/setup/
libraryPath/rev.20070306_1712/cds.lib' for Lib 'c7lite5vhdlui_co'.
\o veriloga Diagnostics: Warnings exist in veriloga text of cell
comparator.
\o Compiling ahdlcmi module library.
\o Failed to compile ahdlcmi module library, see
\o /research2/antara/ICFB/lp3919_c3_10R2/comparator/veriloga/
veriloga.va.ahdlcmi/
\o for details
\o Could not open ahdlcmi module library
\o /research2/antara/ICFB/lp3919_c3_10R2/comparator/veriloga/
veriloga.va.ahdlcmi/obj/Linux2.6.18-92.el5PAE+gcc/optimize/
libahdlcmi.so
\o /research2/antara/ICFB/lp3919_c3_10R2/comparator/veriloga/
veriloga.va.ahdlcmi/obj/Linux2.6.18-92.el5PAE+gcc/optimize/
libahdlcmi.so:
\o cannot open shared object file: No such file or directory
\o Symbol (comparator symbol) generated and saved in
library:lp3919_c3_10R2.
\o Completed generating design in library "lp3919_c3_10R2" as
"comparator" "symbol".
\w *WARNING* The directory: '/designPackages/design_installer/cmos7_5v/
R10.4/libraries/std_cells/c7lite5vhdlui_co/opus_50/c7lite5vhdlui_co'
does not exist
\w but was defined in libFile '/designPackages/design_installer/
cmos7_5v/R10.4/tools/ace/public/cmos7_5v_50/release/cmos7_5v/setup/
libraryPath/rev.20070306_1712/cds.lib' for Lib 'c7lite5vhdlui_co'.
\w *WARNING* The directory: '/designPackages/design_installer/cmos7_5v/
R10.4/libraries/std_cells/c7lite5vhdlui_co/opus_50/c7lite5vhdlui_co'
does not exist
\w but was defined in libFile '/designPackages/design_installer/
cmos7_5v/R10.4/tools/ace/public/cmos7_5v_50/release/cmos7_5v/setup/
libraryPath/rev.20070306_1712/cds.lib' for Lib 'c7lite5vhdlui_co'.
\o veriloga Diagnostics: Warnings exist in veriloga text of cell
sc_flag.
\o Compiling ahdlcmi module library.
\o Failed to compile ahdlcmi module library, see
\o /research2/antara/ICFB/lp3919_c3_10R2/sc_flag/veriloga/
veriloga.va.ahdlcmi/
\o for details
\o Could not open ahdlcmi module library
\o /research2/antara/ICFB/lp3919_c3_10R2/sc_flag/veriloga/
veriloga.va.ahdlcmi/obj/Linux2.6.18-92.el5PAE+gcc/optimize/
libahdlcmi.so
\o /research2/antara/ICFB/lp3919_c3_10R2/sc_flag/veriloga/
veriloga.va.ahdlcmi/obj/Linux2.6.18-92.el5PAE+gcc/optimize/
libahdlcmi.so:
\o cannot open shared object file: No such file or directory
\o Symbol (sc_flag symbol) generated and saved in
library:lp3919_c3_10R2.
\o Completed generating design in library "lp3919_c3_10R2" as
"sc_flag" "symbol".
\w *WARNING* The directory: '/designPackages/design_installer/cmos7_5v/
R10.4/libraries/std_cells/c7lite5vhdlui_co/opus_50/c7lite5vhdlui_co'
does not exist
\w but was defined in libFile '/designPackages/design_installer/
cmos7_5v/R10.4/tools/ace/public/cmos7_5v_50/release/cmos7_5v/setup/
libraryPath/rev.20070306_1712/cds.lib' for Lib 'c7lite5vhdlui_co'.
\w *WARNING* The directory: '/designPackages/design_installer/cmos7_5v/
R10.4/libraries/std_cells/c7lite5vhdlui_co/opus_50/c7lite5vhdlui_co'
does not exist
\w but was defined in libFile '/designPackages/design_installer/
cmos7_5v/R10.4/tools/ace/public/cmos7_5v_50/release/cmos7_5v/setup/
libraryPath/rev.20070306_1712/cds.lib' for Lib 'c7lite5vhdlui_co'.
\o veriloga Diagnostics: Warnings exist in veriloga text of cell
test_ldo_ldod001_c2.
\o Compiling ahdlcmi module library.
\o Failed to compile ahdlcmi module library, see
\o /research2/antara/ICFB/lp3919_c3_10R2/test_ldo_ldod001_c2/
veriloga/veriloga.va.ahdlcmi/
\o for details
\o Could not open ahdlcmi module library
\o /research2/antara/ICFB/lp3919_c3_10R2/test_ldo_ldod001_c2/
veriloga/veriloga.va.ahdlcmi/obj/Linux2.6.18-92.el5PAE+gcc/optimize/
libahdlcmi.so
\o /research2/antara/ICFB/lp3919_c3_10R2/test_ldo_ldod001_c2/
veriloga/veriloga.va.ahdlcmi/obj/Linux2.6.18-92.el5PAE+gcc/optimize/
libahdlcmi.so:
\o cannot open shared object file: No such file or directory
\o Symbol (test_ldo_ldod001_c2 symbol) generated and saved in
library:lp3919_c3_10R2.
\o Completed generating design in library "lp3919_c3_10R2" as
"test_ldo_ldod001_c2" "symbol".
\w *WARNING* The directory: '/designPackages/design_installer/cmos7_5v/
R10.4/libraries/std_cells/c7lite5vhdlui_co/opus_50/c7lite5vhdlui_co'
does not exist
\w but was defined in libFile '/designPackages/design_installer/
cmos7_5v/R10.4/tools/ace/public/cmos7_5v_50/release/cmos7_5v/setup/
libraryPath/rev.20070306_1712/cds.lib' for Lib 'c7lite5vhdlui_co'.
\w *WARNING* The directory: '/designPackages/design_installer/cmos7_5v/
R10.4/libraries/std_cells/c7lite5vhdlui_co/opus_50/c7lite5vhdlui_co'
does not exist
\w but was defined in libFile '/designPackages/design_installer/
cmos7_5v/R10.4/tools/ace/public/cmos7_5v_50/release/cmos7_5v/setup/
libraryPath/rev.20070306_1712/cds.lib' for Lib 'c7lite5vhdlui_co'.
\w *WARNING* The directory: '/designPackages/design_installer/cmos7_5v/
R10.4/libraries/std_cells/c7lite5vhdlui_co/opus_50/c7lite5vhdlui_co'
does not exist
\w but was defined in libFile '/designPackages/design_installer/
cmos7_5v/R10.4/tools/ace/public/cmos7_5v_50/release/cmos7_5v/setup/
libraryPath/rev.20070306_1712/cds.lib' for Lib 'c7lite5vhdlui_co'.
\t t
\p >



It appears that compiler failed to compile some ahdlcmi libraray or
module. Can you please suggest how can I solve this one?
 
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