Bidirectional bus : how to in Verilog

Hi all,
I'm new to Verilog (although I've been designing and repairing electronics since many years).Not being yet familiar with coding I'm porting to Quartus schematics block some designs of mine using the examples (primitives) in the library.There are a couple of designs with bidirectional bus (made by the 74LS245 transceiver) hence I was wondering how to accomplish this in Verilog.Here are snippets of schematics:

https://i.postimg.cc/HLDFnmFZ/bidir.jpg

https://i.postimg.cc/XvfMVrs7/bidir-2.jpg

Any help or suggestion is appreciated.Thanks in advance.

 

[Rick C]

On Tuesday, April 28, 2020 at 2:24:58 PM UTC-4, bri...@gmail.com wrote:

Hi all,
I'm new to Verilog (although I've been designing and repairing electronics since many years).Not being yet familiar with coding I'm porting to Quartus schematics block some designs of mine using the examples (primitives) in the library.There are a couple of designs with bidirectional bus (made by the 74LS245 transceiver) hence I was wondering how to accomplish this in Verilog.Here are snippets of schematics:

https://i.postimg.cc/HLDFnmFZ/bidir.jpg

https://i.postimg.cc/XvfMVrs7/bidir-2.jpg

Any help or suggestion is appreciated.Thanks in advance.

I'm not as conversant in Verilog as VHDL, but in VHDL signals have a value 'Z' which is essentially the high impedance state of a tri-state output. When you want a driver to output the high-impedance state you drive it with a 'Z'.

However, there are few ways to implement such designs. FPGAs no longer contain internal tri-state drivers. They are only in the I/O pins. So an FPGA can hang on an external bus as a tri-state driver, but not internally. I think you won't find many ASIC devices that aren't the same way.

Is this for an external bus?

--

Rick C.

- Get 1,000 miles of free Supercharging
- Tesla referral code - https://ts.la/richard11209

 

On Tuesday, 28 April 2020 20:52:23 UTC+2, Rick C wrote:

On Tuesday, April 28, 2020 at 2:24:58 PM UTC-4, bri...@gmail.com wrote:
Hi all,
I'm new to Verilog (although I've been designing and repairing electronics since many years).Not being yet familiar with coding I'm porting to Quartus schematics block some designs of mine using the examples (primitives) in the library.There are a couple of designs with bidirectional bus (made by the 74LS245 transceiver) hence I was wondering how to accomplish this in Verilog.Here are snippets of schematics:

https://i.postimg.cc/HLDFnmFZ/bidir.jpg

https://i.postimg.cc/XvfMVrs7/bidir-2.jpg

Any help or suggestion is appreciated.Thanks in advance.

I'm not as conversant in Verilog as VHDL, but in VHDL signals have a value 'Z' which is essentially the high impedance state of a tri-state output. When you want a driver to output the high-impedance state you drive it with a 'Z'.

However, there are few ways to implement such designs. FPGAs no longer contain internal tri-state drivers. They are only in the I/O pins. So an FPGA can hang on an external bus as a tri-state driver, but not internally. I think you won't find many ASIC devices that aren't the same way.

Is this for an external bus?

--

Rick C.

- Get 1,000 miles of free Supercharging
- Tesla referral code - https://ts.la/richard11209

Thanks for reply.I forgot to say that I want to implement the logics in old CPLD (+5V tolerant Altera or Atmel).The bus is external and, since there is no 74245 in the Quartus library, I made my own but I think it's not working good as I get crash in the system.Hence, I'm also considering to use external 74245 devices and embed the rest of the logics in the CPLD.

 

[Richard Damon]

On 4/28/20 3:40 PM, briccus@gmail.com wrote:

On Tuesday, 28 April 2020 20:52:23 UTC+2, Rick C wrote:
On Tuesday, April 28, 2020 at 2:24:58 PM UTC-4, bri...@gmail.com wrote:
Hi all,
I'm new to Verilog (although I've been designing and repairing electronics since many years).Not being yet familiar with coding I'm porting to Quartus schematics block some designs of mine using the examples (primitives) in the library.There are a couple of designs with bidirectional bus (made by the 74LS245 transceiver) hence I was wondering how to accomplish this in Verilog.Here are snippets of schematics:

https://i.postimg.cc/HLDFnmFZ/bidir.jpg

https://i.postimg.cc/XvfMVrs7/bidir-2.jpg

Any help or suggestion is appreciated.Thanks in advance.

I'm not as conversant in Verilog as VHDL, but in VHDL signals have a value 'Z' which is essentially the high impedance state of a tri-state output. When you want a driver to output the high-impedance state you drive it with a 'Z'.

However, there are few ways to implement such designs. FPGAs no longer contain internal tri-state drivers. They are only in the I/O pins. So an FPGA can hang on an external bus as a tri-state driver, but not internally. I think you won't find many ASIC devices that aren't the same way.

Is this for an external bus?

--

Rick C.

- Get 1,000 miles of free Supercharging
- Tesla referral code - https://ts.la/richard11209

Thanks for reply.I forgot to say that I want to implement the logics in old CPLD (+5V tolerant Altera or Atmel).The bus is external and, since there is no 74245 in the Quartus library, I made my own but I think it's not working good as I get crash in the system.Hence, I'm also considering to use external 74245 devices and embed the rest of the logics in the CPLD.

Verilog driving with logic state 'z' should synthesize into a tri-state
driver, or there should be a Tristate macro function you can explicitly
instantiate for the output pin.

 

[Rick C]

On Tuesday, April 28, 2020 at 3:40:40 PM UTC-4, bri...@gmail.com wrote:

On Tuesday, 28 April 2020 20:52:23 UTC+2, Rick C wrote:
On Tuesday, April 28, 2020 at 2:24:58 PM UTC-4, bri...@gmail.com wrote:
Hi all,
I'm new to Verilog (although I've been designing and repairing electronics since many years).Not being yet familiar with coding I'm porting to Quartus schematics block some designs of mine using the examples (primitives) in the library.There are a couple of designs with bidirectional bus (made by the 74LS245 transceiver) hence I was wondering how to accomplish this in Verilog.Here are snippets of schematics:

https://i.postimg.cc/HLDFnmFZ/bidir.jpg

https://i.postimg.cc/XvfMVrs7/bidir-2.jpg

Any help or suggestion is appreciated.Thanks in advance.

I'm not as conversant in Verilog as VHDL, but in VHDL signals have a value 'Z' which is essentially the high impedance state of a tri-state output.. When you want a driver to output the high-impedance state you drive it with a 'Z'.

However, there are few ways to implement such designs. FPGAs no longer contain internal tri-state drivers. They are only in the I/O pins. So an FPGA can hang on an external bus as a tri-state driver, but not internally.. I think you won't find many ASIC devices that aren't the same way.

Is this for an external bus?

--

Rick C.

- Get 1,000 miles of free Supercharging
- Tesla referral code - https://ts.la/richard11209

Thanks for reply.I forgot to say that I want to implement the logics in old CPLD (+5V tolerant Altera or Atmel).The bus is external and, since there is no 74245 in the Quartus library, I made my own but I think it's not working good as I get crash in the system.Hence, I'm also considering to use external 74245 devices and embed the rest of the logics in the CPLD.

A crash in what system, the tools or your hardware?

Why don't you paste your '245 model code? It can't be very much code. It should be less than half a dozen lines. In VHDL this would be one line of code depending on the length of your signal names.

IO_bus <= (others => 'Z') when Tristate_En = '0' else Internal_bus;

I imagine the Verilog is very similar.

--

Rick C.

+ Get 1,000 miles of free Supercharging
+ Tesla referral code - https://ts.la/richard11209

 

On Tuesday, 28 April 2020 22:31:55 UTC+2, Rick C wrote:

On Tuesday, April 28, 2020 at 3:40:40 PM UTC-4, bri...@gmail.com wrote:
On Tuesday, 28 April 2020 20:52:23 UTC+2, Rick C wrote:
On Tuesday, April 28, 2020 at 2:24:58 PM UTC-4, bri...@gmail.com wrote:
Hi all,
I'm new to Verilog (although I've been designing and repairing electronics since many years).Not being yet familiar with coding I'm porting to Quartus schematics block some designs of mine using the examples (primitives) in the library.There are a couple of designs with bidirectional bus (made by the 74LS245 transceiver) hence I was wondering how to accomplish this in Verilog.Here are snippets of schematics:

https://i.postimg.cc/HLDFnmFZ/bidir.jpg

https://i.postimg.cc/XvfMVrs7/bidir-2.jpg

Any help or suggestion is appreciated.Thanks in advance.

I'm not as conversant in Verilog as VHDL, but in VHDL signals have a value 'Z' which is essentially the high impedance state of a tri-state output. When you want a driver to output the high-impedance state you drive it with a 'Z'.

However, there are few ways to implement such designs. FPGAs no longer contain internal tri-state drivers. They are only in the I/O pins. So an FPGA can hang on an external bus as a tri-state driver, but not internally. I think you won't find many ASIC devices that aren't the same way.

Is this for an external bus?

--

Rick C.

- Get 1,000 miles of free Supercharging
- Tesla referral code - https://ts.la/richard11209

Thanks for reply.I forgot to say that I want to implement the logics in old CPLD (+5V tolerant Altera or Atmel).The bus is external and, since there is no 74245 in the Quartus library, I made my own but I think it's not working good as I get crash in the system.Hence, I'm also considering to use external 74245 devices and embed the rest of the logics in the CPLD.

A crash in what system, the tools or your hardware?

Why don't you paste your '245 model code? It can't be very much code. It should be less than half a dozen lines. In VHDL this would be one line of code depending on the length of your signal names.

IO_bus <= (others => 'Z') when Tristate_En = '0' else Internal_bus;

I imagine the Verilog is very similar.

--

Rick C.

+ Get 1,000 miles of free Supercharging
+ Tesla referral code - https://ts.la/richard11209

Well, as i said I'm not yer familiar with writing code so I ported to Quartus the logic diagram of the 74245 (from whatever datasheet) and made a BDF file (and a BSF too for the symbol) :

http://www.mediafire.com/file/5evap6f2lmq7mq5/IC74245.bdf/file


I also found a couple of Verilog implementation of the 74245 :

Library ieee;
Use ieee.std_logic_1164.all;

Entity VHDL_74245 is
Port(G_L,DIR: in std_logic;
A,B: inout std_logic_vector(7 downto 0);
Y: out std_logic_vector(7 downto 0));
End VHDL_74245;

Architecture behav of VHDL_74245 is
Begin
Process (G_L, DIR, A,B)
Begin
If(G_L='0' and DIR='1') then
B<=A;
Elsif (G_L='0' and DIR='0') then
A<=B;
End if;
End process;
End behav;


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;


entity CPLD_74LS245 is
Port ( nE : in STD_LOGIC;
dir : in STD_LOGIC;
B : inout STD_LOGIC_VECTOR (7 downto 0);
A : inout STD_LOGIC_VECTOR (7 downto 0));
end CPLD_74LS245;

architecture Behavioral of CPLD_74LS245 is
begin

-- Wenn nE = 1 oder dir = '1' dann HighZ
-- Sonst B
A <= (7 downto 0 => 'Z') when nE = '1' OR dir = '1' else B;

-- Wenn nE = 1 oder dir = '1' dann HighZ
-- Sonst A
B <= (7 downto 0 => 'Z') when nE = '1' OR dir = '0' else A;

end Behavioral;

 

[Rick C]

On Tuesday, April 28, 2020 at 5:39:47 PM UTC-4, bri...@gmail.com wrote:

On Tuesday, 28 April 2020 22:31:55 UTC+2, Rick C wrote:
On Tuesday, April 28, 2020 at 3:40:40 PM UTC-4, bri...@gmail.com wrote:
On Tuesday, 28 April 2020 20:52:23 UTC+2, Rick C wrote:
On Tuesday, April 28, 2020 at 2:24:58 PM UTC-4, bri...@gmail.com wrote:
Hi all,
I'm new to Verilog (although I've been designing and repairing electronics since many years).Not being yet familiar with coding I'm porting to Quartus schematics block some designs of mine using the examples (primitives) in the library.There are a couple of designs with bidirectional bus (made by the 74LS245 transceiver) hence I was wondering how to accomplish this in Verilog.Here are snippets of schematics:

https://i.postimg.cc/HLDFnmFZ/bidir.jpg

https://i.postimg.cc/XvfMVrs7/bidir-2.jpg

Any help or suggestion is appreciated.Thanks in advance.

I'm not as conversant in Verilog as VHDL, but in VHDL signals have a value 'Z' which is essentially the high impedance state of a tri-state output. When you want a driver to output the high-impedance state you drive it with a 'Z'.

However, there are few ways to implement such designs. FPGAs no longer contain internal tri-state drivers. They are only in the I/O pins. So an FPGA can hang on an external bus as a tri-state driver, but not internally. I think you won't find many ASIC devices that aren't the same way.

Is this for an external bus?

--

Rick C.

- Get 1,000 miles of free Supercharging
- Tesla referral code - https://ts.la/richard11209

Thanks for reply.I forgot to say that I want to implement the logics in old CPLD (+5V tolerant Altera or Atmel).The bus is external and, since there is no 74245 in the Quartus library, I made my own but I think it's not working good as I get crash in the system.Hence, I'm also considering to use external 74245 devices and embed the rest of the logics in the CPLD.

A crash in what system, the tools or your hardware?

Why don't you paste your '245 model code? It can't be very much code. It should be less than half a dozen lines. In VHDL this would be one line of code depending on the length of your signal names.

IO_bus <= (others => 'Z') when Tristate_En = '0' else Internal_bus;

I imagine the Verilog is very similar.

--

Rick C.

+ Get 1,000 miles of free Supercharging
+ Tesla referral code - https://ts.la/richard11209

Well, as i said I'm not yer familiar with writing code so I ported to Quartus the logic diagram of the 74245 (from whatever datasheet) and made a BDF file (and a BSF too for the symbol) :

http://www.mediafire.com/file/5evap6f2lmq7mq5/IC74245.bdf/file


I also found a couple of Verilog implementation of the 74245 :

Library ieee;
Use ieee.std_logic_1164.all;

Entity VHDL_74245 is
Port(G_L,DIR: in std_logic;
A,B: inout std_logic_vector(7 downto 0);
Y: out std_logic_vector(7 downto 0));
End VHDL_74245;

Architecture behav of VHDL_74245 is
Begin
Process (G_L, DIR, A,B)
Begin
If(G_L='0' and DIR='1') then
B<=A;
Elsif (G_L='0' and DIR='0') then
A<=B;
End if;
End process;
End behav;


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;


entity CPLD_74LS245 is
Port ( nE : in STD_LOGIC;
dir : in STD_LOGIC;
B : inout STD_LOGIC_VECTOR (7 downto 0);
A : inout STD_LOGIC_VECTOR (7 downto 0));
end CPLD_74LS245;

architecture Behavioral of CPLD_74LS245 is
begin

-- Wenn nE = 1 oder dir = '1' dann HighZ
-- Sonst B
A <= (7 downto 0 => 'Z') when nE = '1' OR dir = '1' else B;

-- Wenn nE = 1 oder dir = '1' dann HighZ
-- Sonst A
B <= (7 downto 0 => 'Z') when nE = '1' OR dir = '0' else A;

end Behavioral;

Your .BDF file is a schematic file format and I don't have a viewer for it. Can you generate an image file or PDF file of your schematic?

The other two implementations are VHDL, not Verilog.

The first looks like it is intended to be used at a chip interface, but is not complete and in fact would generate a latch.

The second is complete but will need to use tristate drivers on both sides of the unit. Are you trying to make a '245 device in a CPLD or are you putting logic in the CPLD and you need to interface the design to a bi-dir tristate bus?

Can you point me to the source of the design you want to implement?

The I/Os of a CPLD or FPGA have to split the bus in two like this.

+------< OE
|
External /|
Tri-state +-----< |-----< A
| \|
Y <<>>-----+ CPLD
| |\
Bus +-----| >-----> B
|/

I don't know of any TTL devices that do this. If you can use VHDL code I can give you a VHDL module that will do this. I need to see your full design to tell if this is what you need or how to adapt it.

--

Rick C.

-- Get 1,000 miles of free Supercharging
-- Tesla referral code - https://ts.la/richard11209

 

[Rick C]

Just so you know. If the ascii art drawing looks like gibberish you need to view it in a mono-spaced font.

Here is some (untested) VHDL to implement the buffer you need for the outside world. I'm sitting here bored, so thought I'd do something useful.

-- A is an input from the FPGA/CPLD innards
-- B is output to the FPGA/CPLD innards,
-- Y is external bidir
-- OE is a high true output enable
signal A, B, Y std_logic_vector (7 downto 0);

io_buf: process(A,Y,OE) begin
if (OE = '1') then
Y = A;
else
Y = 'Z';
end if;

B = Y;
end process io_buf;

io_buf is just a label which is optional. Even if you give it a label adding the label at the end is always optional.

A process is not a subroutine. The list of inputs are not like the inputs/outputs of a subroutine. They are always inputs that will cause the process to "run". In VHDL2008 you can replace that list with an asterisk. If you want something modular to be used in multiple places you can make it a procedure or an entity. A procedure IS a subroutine. An entity is a module that is instantiated (connected to the rest of the circuit through a port map, i.e. a wire list).

io_buf: procedure (
signal A : in std_logic_vector(7 downto 0);
signal B : out std_logic_vector(7 downto 0);
signal Y : inout std_logic_vector(7 downto 0);
signal OE : in std_logic ) is
begin
if (OE = '1') then
Y = A;
else
Y = 'Z';
end if;

B = Y;
end procedure io_buf;


The simplest way to do this is to just use concurrent statements (the simplest type of VHDL. You don't really need the B bus at all since it is just the Y bus from the outside. So the only assignment you need is to drive the output bus to a high-Z state when you aren't driving data.

Y <= 'Z' when (OE = '0') else A;

You can add this if it is more clear

B <= Y;

Sorry if this doesn't help you. I was bored and it was useful for me to review.

--

Rick C.

-+ Get 1,000 miles of free Supercharging
-+ Tesla referral code - https://ts.la/richard11209

 

On Wednesday, 29 April 2020 06:43:32 UTC+2, Rick C wrote:

Just so you know. If the ascii art drawing looks like gibberish you need to view it in a mono-spaced font.

Here is some (untested) VHDL to implement the buffer you need for the outside world. I'm sitting here bored, so thought I'd do something useful.

-- A is an input from the FPGA/CPLD innards
-- B is output to the FPGA/CPLD innards,
-- Y is external bidir
-- OE is a high true output enable
signal A, B, Y std_logic_vector (7 downto 0);

io_buf: process(A,Y,OE) begin
if (OE = '1') then
Y = A;
else
Y = 'Z';
end if;

B = Y;
end process io_buf;

io_buf is just a label which is optional. Even if you give it a label adding the label at the end is always optional.

A process is not a subroutine. The list of inputs are not like the inputs/outputs of a subroutine. They are always inputs that will cause the process to "run". In VHDL2008 you can replace that list with an asterisk. If you want something modular to be used in multiple places you can make it a procedure or an entity. A procedure IS a subroutine. An entity is a module that is instantiated (connected to the rest of the circuit through a port map, i.e. a wire list).

io_buf: procedure (
signal A : in std_logic_vector(7 downto 0);
signal B : out std_logic_vector(7 downto 0);
signal Y : inout std_logic_vector(7 downto 0);
signal OE : in std_logic ) is
begin
if (OE = '1') then
Y = A;
else
Y = 'Z';
end if;

B = Y;
end procedure io_buf;


The simplest way to do this is to just use concurrent statements (the simplest type of VHDL. You don't really need the B bus at all since it is just the Y bus from the outside. So the only assignment you need is to drive the output bus to a high-Z state when you aren't driving data.

Y <= 'Z' when (OE = '0') else A;

You can add this if it is more clear

B <= Y;

Sorry if this doesn't help you. I was bored and it was useful for me to review.

--

Rick C.

-+ Get 1,000 miles of free Supercharging
-+ Tesla referral code - https://ts.la/richard11209

Thanks for spending your time on this.
Yes, I know the two examples of the 74245 I posted are in VHDL and not in Verilog, anyway I think I can use both languages in my Quartus design.
Here is the logic diagram of my 74245 implementation (yes, I want to make this device in my CPLD design) :

http://www.mediafire.com/file/q8qspgz60nfpqum/IC74245.pdf/file

Here's the whole design, it's a simple circuit made of few TTLs gates (with a socket that plugs into the hosting hardware)

http://www.mediafire.com/file/arry2cio0l2g3aw/design.pdf/file

 

[Rick C]

On Wednesday, April 29, 2020 at 5:11:25 AM UTC-4, bri...@gmail.com wrote:

On Wednesday, 29 April 2020 06:43:32 UTC+2, Rick C wrote:
Just so you know. If the ascii art drawing looks like gibberish you need to view it in a mono-spaced font.

Here is some (untested) VHDL to implement the buffer you need for the outside world. I'm sitting here bored, so thought I'd do something useful.

-- A is an input from the FPGA/CPLD innards
-- B is output to the FPGA/CPLD innards,
-- Y is external bidir
-- OE is a high true output enable
signal A, B, Y std_logic_vector (7 downto 0);

io_buf: process(A,Y,OE) begin
if (OE = '1') then
Y = A;
else
Y = 'Z';
end if;

B = Y;
end process io_buf;

io_buf is just a label which is optional. Even if you give it a label adding the label at the end is always optional.

A process is not a subroutine. The list of inputs are not like the inputs/outputs of a subroutine. They are always inputs that will cause the process to "run". In VHDL2008 you can replace that list with an asterisk. If you want something modular to be used in multiple places you can make it a procedure or an entity. A procedure IS a subroutine. An entity is a module that is instantiated (connected to the rest of the circuit through a port map, i.e. a wire list).

io_buf: procedure (
signal A : in std_logic_vector(7 downto 0);
signal B : out std_logic_vector(7 downto 0);
signal Y : inout std_logic_vector(7 downto 0);
signal OE : in std_logic ) is
begin
if (OE = '1') then
Y = A;
else
Y = 'Z';
end if;

B = Y;
end procedure io_buf;


The simplest way to do this is to just use concurrent statements (the simplest type of VHDL. You don't really need the B bus at all since it is just the Y bus from the outside. So the only assignment you need is to drive the output bus to a high-Z state when you aren't driving data.

Y <= 'Z' when (OE = '0') else A;

You can add this if it is more clear

B <= Y;

Sorry if this doesn't help you. I was bored and it was useful for me to review.

--

Rick C.

-+ Get 1,000 miles of free Supercharging
-+ Tesla referral code - https://ts.la/richard11209

Thanks for spending your time on this.
Yes, I know the two examples of the 74245 I posted are in VHDL and not in Verilog, anyway I think I can use both languages in my Quartus design.
Here is the logic diagram of my 74245 implementation (yes, I want to make this device in my CPLD design) :

http://www.mediafire.com/file/q8qspgz60nfpqum/IC74245.pdf/file

Here's the whole design, it's a simple circuit made of few TTLs gates (with a socket that plugs into the hosting hardware)

http://www.mediafire.com/file/arry2cio0l2g3aw/design.pdf/file

I don't know if you can duplicate a '245 device in a 20 pin CPLD. That will require 16 outputs and I don't think they make 20 CPLDs with 20 outputs.

Why can't you just use a 74LS245 device? They are still made. Mouser has them in stock for less than a dollar.

--

Rick C.

+- Get 1,000 miles of free Supercharging
+- Tesla referral code - https://ts.la/richard11209

 

[Rick C]

On Wednesday, April 29, 2020 at 6:33:29 AM UTC-4, Rick C wrote:

On Wednesday, April 29, 2020 at 5:11:25 AM UTC-4, bri...@gmail.com wrote:
On Wednesday, 29 April 2020 06:43:32 UTC+2, Rick C wrote:
Just so you know. If the ascii art drawing looks like gibberish you need to view it in a mono-spaced font.

Here is some (untested) VHDL to implement the buffer you need for the outside world. I'm sitting here bored, so thought I'd do something useful..

-- A is an input from the FPGA/CPLD innards
-- B is output to the FPGA/CPLD innards,
-- Y is external bidir
-- OE is a high true output enable
signal A, B, Y std_logic_vector (7 downto 0);

io_buf: process(A,Y,OE) begin
if (OE = '1') then
Y = A;
else
Y = 'Z';
end if;

B = Y;
end process io_buf;

io_buf is just a label which is optional. Even if you give it a label adding the label at the end is always optional.

A process is not a subroutine. The list of inputs are not like the inputs/outputs of a subroutine. They are always inputs that will cause the process to "run". In VHDL2008 you can replace that list with an asterisk. If you want something modular to be used in multiple places you can make it a procedure or an entity. A procedure IS a subroutine. An entity is a module that is instantiated (connected to the rest of the circuit through a port map, i.e. a wire list).

io_buf: procedure (
signal A : in std_logic_vector(7 downto 0);
signal B : out std_logic_vector(7 downto 0);
signal Y : inout std_logic_vector(7 downto 0);
signal OE : in std_logic ) is
begin
if (OE = '1') then
Y = A;
else
Y = 'Z';
end if;

B = Y;
end procedure io_buf;


The simplest way to do this is to just use concurrent statements (the simplest type of VHDL. You don't really need the B bus at all since it is just the Y bus from the outside. So the only assignment you need is to drive the output bus to a high-Z state when you aren't driving data.

Y <= 'Z' when (OE = '0') else A;

You can add this if it is more clear

B <= Y;

Sorry if this doesn't help you. I was bored and it was useful for me to review.

--

Rick C.

-+ Get 1,000 miles of free Supercharging
-+ Tesla referral code - https://ts.la/richard11209

Thanks for spending your time on this.
Yes, I know the two examples of the 74245 I posted are in VHDL and not in Verilog, anyway I think I can use both languages in my Quartus design.
Here is the logic diagram of my 74245 implementation (yes, I want to make this device in my CPLD design) :

http://www.mediafire.com/file/q8qspgz60nfpqum/IC74245.pdf/file

Here's the whole design, it's a simple circuit made of few TTLs gates (with a socket that plugs into the hosting hardware)

http://www.mediafire.com/file/arry2cio0l2g3aw/design.pdf/file

I don't know if you can duplicate a '245 device in a 20 pin CPLD. That will require 16 outputs and I don't think they make 20 CPLDs with 20 outputs..

Sorry, I meant I don't think they make 20 pin CPLDs with 16 outputs.

 

On Wednesday, 29 April 2020 12:33:29 UTC+2, Rick C wrote:

On Wednesday, April 29, 2020 at 5:11:25 AM UTC-4, bri...@gmail.com wrote:
On Wednesday, 29 April 2020 06:43:32 UTC+2, Rick C wrote:
Just so you know. If the ascii art drawing looks like gibberish you need to view it in a mono-spaced font.

Here is some (untested) VHDL to implement the buffer you need for the outside world. I'm sitting here bored, so thought I'd do something useful..

-- A is an input from the FPGA/CPLD innards
-- B is output to the FPGA/CPLD innards,
-- Y is external bidir
-- OE is a high true output enable
signal A, B, Y std_logic_vector (7 downto 0);

io_buf: process(A,Y,OE) begin
if (OE = '1') then
Y = A;
else
Y = 'Z';
end if;

B = Y;
end process io_buf;

io_buf is just a label which is optional. Even if you give it a label adding the label at the end is always optional.

A process is not a subroutine. The list of inputs are not like the inputs/outputs of a subroutine. They are always inputs that will cause the process to "run". In VHDL2008 you can replace that list with an asterisk. If you want something modular to be used in multiple places you can make it a procedure or an entity. A procedure IS a subroutine. An entity is a module that is instantiated (connected to the rest of the circuit through a port map, i.e. a wire list).

io_buf: procedure (
signal A : in std_logic_vector(7 downto 0);
signal B : out std_logic_vector(7 downto 0);
signal Y : inout std_logic_vector(7 downto 0);
signal OE : in std_logic ) is
begin
if (OE = '1') then
Y = A;
else
Y = 'Z';
end if;

B = Y;
end procedure io_buf;


The simplest way to do this is to just use concurrent statements (the simplest type of VHDL. You don't really need the B bus at all since it is just the Y bus from the outside. So the only assignment you need is to drive the output bus to a high-Z state when you aren't driving data.

Y <= 'Z' when (OE = '0') else A;

You can add this if it is more clear

B <= Y;

Sorry if this doesn't help you. I was bored and it was useful for me to review.

--

Rick C.

-+ Get 1,000 miles of free Supercharging
-+ Tesla referral code - https://ts.la/richard11209

Thanks for spending your time on this.
Yes, I know the two examples of the 74245 I posted are in VHDL and not in Verilog, anyway I think I can use both languages in my Quartus design.
Here is the logic diagram of my 74245 implementation (yes, I want to make this device in my CPLD design) :

http://www.mediafire.com/file/q8qspgz60nfpqum/IC74245.pdf/file

Here's the whole design, it's a simple circuit made of few TTLs gates (with a socket that plugs into the hosting hardware)

http://www.mediafire.com/file/arry2cio0l2g3aw/design.pdf/file

I don't know if you can duplicate a '245 device in a 20 pin CPLD. That will require 16 outputs and I don't think they make 20 CPLDs with 20 outputs..

Why can't you just use a 74LS245 device? They are still made. Mouser has them in stock for less than a dollar.

--

Rick C.

+- Get 1,000 miles of free Supercharging
+- Tesla referral code - https://ts.la/richard11209

I explained myself bad, sorry.I want to port into a CPLD the schematics I attached in which there is a 74245, not doing a CPLD version of the 74245.And yes, I have considered to use an external 74245 instead of implenting it in the Quartus CPLD design whereas all the remaining logics you can see in the attached schematics will be implemented in the CPLD.

 

On Wednesday, 29 April 2020 12:42:05 UTC+2, bri...@gmail.com wrote:

On Wednesday, 29 April 2020 12:33:29 UTC+2, Rick C wrote:
On Wednesday, April 29, 2020 at 5:11:25 AM UTC-4, bri...@gmail.com wrote:
On Wednesday, 29 April 2020 06:43:32 UTC+2, Rick C wrote:
Just so you know. If the ascii art drawing looks like gibberish you need to view it in a mono-spaced font.

Here is some (untested) VHDL to implement the buffer you need for the outside world. I'm sitting here bored, so thought I'd do something useful.

-- A is an input from the FPGA/CPLD innards
-- B is output to the FPGA/CPLD innards,
-- Y is external bidir
-- OE is a high true output enable
signal A, B, Y std_logic_vector (7 downto 0);

io_buf: process(A,Y,OE) begin
if (OE = '1') then
Y = A;
else
Y = 'Z';
end if;

B = Y;
end process io_buf;

io_buf is just a label which is optional. Even if you give it a label adding the label at the end is always optional.

A process is not a subroutine. The list of inputs are not like the inputs/outputs of a subroutine. They are always inputs that will cause the process to "run". In VHDL2008 you can replace that list with an asterisk.. If you want something modular to be used in multiple places you can make it a procedure or an entity. A procedure IS a subroutine. An entity is a module that is instantiated (connected to the rest of the circuit through a port map, i.e. a wire list).

io_buf: procedure (
signal A : in std_logic_vector(7 downto 0);
signal B : out std_logic_vector(7 downto 0);
signal Y : inout std_logic_vector(7 downto 0);
signal OE : in std_logic ) is
begin
if (OE = '1') then
Y = A;
else
Y = 'Z';
end if;

B = Y;
end procedure io_buf;


The simplest way to do this is to just use concurrent statements (the simplest type of VHDL. You don't really need the B bus at all since it is just the Y bus from the outside. So the only assignment you need is to drive the output bus to a high-Z state when you aren't driving data.

Y <= 'Z' when (OE = '0') else A;

You can add this if it is more clear

B <= Y;

Sorry if this doesn't help you. I was bored and it was useful for me to review.

--

Rick C.

-+ Get 1,000 miles of free Supercharging
-+ Tesla referral code - https://ts.la/richard11209

Thanks for spending your time on this.
Yes, I know the two examples of the 74245 I posted are in VHDL and not in Verilog, anyway I think I can use both languages in my Quartus design.
Here is the logic diagram of my 74245 implementation (yes, I want to make this device in my CPLD design) :

http://www.mediafire.com/file/q8qspgz60nfpqum/IC74245.pdf/file

Here's the whole design, it's a simple circuit made of few TTLs gates (with a socket that plugs into the hosting hardware)

http://www.mediafire.com/file/arry2cio0l2g3aw/design.pdf/file

I don't know if you can duplicate a '245 device in a 20 pin CPLD. That will require 16 outputs and I don't think they make 20 CPLDs with 20 outputs.

Why can't you just use a 74LS245 device? They are still made. Mouser has them in stock for less than a dollar.

--

Rick C.

+- Get 1,000 miles of free Supercharging
+- Tesla referral code - https://ts.la/richard11209

I explained myself bad, sorry.I want to port into a CPLD the schematics I attached in which there is a 74245, not doing a CPLD version of the 74245..And yes, I have considered to use an external 74245 instead of implenting it in the Quartus CPLD design whereas all the remaining logics you can see in the attached schematics will be implemented in the CPLD.

I forgot.As CPLD I will use a +5V Altera EPM7128 (TQFP100) with 84 I/O and 128 macrocells.I already successfully used it in other my projects.

 

[Kevin Neilson]

On Tuesday, April 28, 2020 at 12:24:58 PM UTC-6, bri...@gmail.com wrote:

Hi all,
I'm new to Verilog (although I've been designing and repairing electronics since many years).Not being yet familiar with coding I'm porting to Quartus schematics block some designs of mine using the examples (primitives) in the library.There are a couple of designs with bidirectional bus (made by the 74LS245 transceiver) hence I was wondering how to accomplish this in Verilog.

I haven't used tristates in quite a while, but as I recall, it goes something like this:

inout [7:0] tristate_bus, // declare tristates as inout ports
...

reg [7:0] data_out; // data to be driven onto tristate_bus
reg output_en; // 1=>drive data_out onto tristate_bus
assign tristate_bus = output_en ? data_out : 'bz; // high-Z when output_en=0
wire [7:0] read_data = tristate_bus; // data read from tristate bus

 

[Rick C]

On Wednesday, April 29, 2020 at 6:44:37 AM UTC-4, bri...@gmail.com wrote:

On Wednesday, 29 April 2020 12:42:05 UTC+2, bri...@gmail.com wrote:
On Wednesday, 29 April 2020 12:33:29 UTC+2, Rick C wrote:
On Wednesday, April 29, 2020 at 5:11:25 AM UTC-4, bri...@gmail.com wrote:
On Wednesday, 29 April 2020 06:43:32 UTC+2, Rick C wrote:
Just so you know. If the ascii art drawing looks like gibberish you need to view it in a mono-spaced font.

Here is some (untested) VHDL to implement the buffer you need for the outside world. I'm sitting here bored, so thought I'd do something useful.

-- A is an input from the FPGA/CPLD innards
-- B is output to the FPGA/CPLD innards,
-- Y is external bidir
-- OE is a high true output enable
signal A, B, Y std_logic_vector (7 downto 0);

io_buf: process(A,Y,OE) begin
if (OE = '1') then
Y = A;
else
Y = 'Z';
end if;

B = Y;
end process io_buf;

io_buf is just a label which is optional. Even if you give it a label adding the label at the end is always optional.

A process is not a subroutine. The list of inputs are not like the inputs/outputs of a subroutine. They are always inputs that will cause the process to "run". In VHDL2008 you can replace that list with an asterisk. If you want something modular to be used in multiple places you can make it a procedure or an entity. A procedure IS a subroutine. An entity is a module that is instantiated (connected to the rest of the circuit through a port map, i.e. a wire list).

io_buf: procedure (
signal A : in std_logic_vector(7 downto 0);
signal B : out std_logic_vector(7 downto 0);
signal Y : inout std_logic_vector(7 downto 0);
signal OE : in std_logic ) is
begin
if (OE = '1') then
Y = A;
else
Y = 'Z';
end if;

B = Y;
end procedure io_buf;


The simplest way to do this is to just use concurrent statements (the simplest type of VHDL. You don't really need the B bus at all since it is just the Y bus from the outside. So the only assignment you need is to drive the output bus to a high-Z state when you aren't driving data.

Y <= 'Z' when (OE = '0') else A;

You can add this if it is more clear

B <= Y;

Sorry if this doesn't help you. I was bored and it was useful for me to review.

--

Rick C.

-+ Get 1,000 miles of free Supercharging
-+ Tesla referral code - https://ts.la/richard11209

Thanks for spending your time on this.
Yes, I know the two examples of the 74245 I posted are in VHDL and not in Verilog, anyway I think I can use both languages in my Quartus design.
Here is the logic diagram of my 74245 implementation (yes, I want to make this device in my CPLD design) :

http://www.mediafire.com/file/q8qspgz60nfpqum/IC74245.pdf/file

Here's the whole design, it's a simple circuit made of few TTLs gates (with a socket that plugs into the hosting hardware)

http://www.mediafire.com/file/arry2cio0l2g3aw/design.pdf/file

I don't know if you can duplicate a '245 device in a 20 pin CPLD. That will require 16 outputs and I don't think they make 20 CPLDs with 20 outputs.

Why can't you just use a 74LS245 device? They are still made. Mouser has them in stock for less than a dollar.

--

Rick C.

+- Get 1,000 miles of free Supercharging
+- Tesla referral code - https://ts.la/richard11209

I explained myself bad, sorry.I want to port into a CPLD the schematics I attached in which there is a 74245, not doing a CPLD version of the 74245.And yes, I have considered to use an external 74245 instead of implenting it in the Quartus CPLD design whereas all the remaining logics you can see in the attached schematics will be implemented in the CPLD.

I forgot.As CPLD I will use a +5V Altera EPM7128 (TQFP100) with 84 I/O and 128 macrocells.I already successfully used it in other my projects.

Ok, that is more clear. I will say the EPM7128 is very much overkill for this design, but that's ok. Better too large than too small. So the code I gave you should do the job here is an example that does the full in and out of the '245. One I/O is A and the other B as in your schematic.


signal DA, DB : std_logic_vector (7 downto 0);
signal s402_2H, s401_fi, other_ck, s601 : std_logic;
signal RD_n, s603, s602, wait_n, FF1, FF2 : std_logic;

DA <= 'Z' when (s602 or RD_n = '1') else DB;
DB <= 'Z' when (s602 or not RD_n = '1') else DA;

wait_n <= not 402_2H or s601;
s602 <= FF1 and FF2 or s601;
s603 <= s602 or not RD_n;

process (other_ck, 402_2H_n) begin
if (402_2H = '1') then
FF1 <= '1';
elsif (rising_edge(other_ck))
FF1 <= s401_fi;
end if;

if (falling_edge(other_ck))
FF2 <= FF1;
end if;
end process;

This is the logic as shown on the page. It still needs the entity boilerplate to define the I/Os for the device which are the signals on the 28 pin connector.

Can you tell me what the design does? The '245 device seems to simple connect pins on the 28 pin socket back to itself, either in one direction or the other. What plugs into the socket??? It would appear to be an MCU which makes little sense to tie 8 lines back to themselves. Or maybe you are trying to replace one of the higher complexity bus interface devices that aren't made anymore?

There are a couple of parts of the schematic that are troubling. One is the use of the PREset pin on the FF. PREset and CLR are asynchronous logic (combinational) and have very particular timing constraints which will be very different inside the CPLD and a TTL device. Without a thorough understanding of the design it is hard to know if this will work well. It is better to use the synchronous logic with separate combinational logic. That can only be done with detailed info on the intended operation of the device.

The same thing applies to the use of two inverters to create the enable on the '245 device. This is a logic noop which will only create an ill defined delay. This is hard to do in a CPLD since the tools will optimize it out.. It has the same timing concerns as the PREset on the FF.

The more info you can provide, the more help you can get.

--

Rick C.

++ Get 1,000 miles of free Supercharging
++ Tesla referral code - https://ts.la/richard11209

 

On Wednesday, 29 April 2020 21:48:55 UTC+2, Rick C wrote:

On Wednesday, April 29, 2020 at 6:44:37 AM UTC-4, bri...@gmail.com wrote:
On Wednesday, 29 April 2020 12:42:05 UTC+2, bri...@gmail.com wrote:
On Wednesday, 29 April 2020 12:33:29 UTC+2, Rick C wrote:
On Wednesday, April 29, 2020 at 5:11:25 AM UTC-4, bri...@gmail.com wrote:
On Wednesday, 29 April 2020 06:43:32 UTC+2, Rick C wrote:
Just so you know. If the ascii art drawing looks like gibberish you need to view it in a mono-spaced font.

Here is some (untested) VHDL to implement the buffer you need for the outside world. I'm sitting here bored, so thought I'd do something useful.

-- A is an input from the FPGA/CPLD innards
-- B is output to the FPGA/CPLD innards,
-- Y is external bidir
-- OE is a high true output enable
signal A, B, Y std_logic_vector (7 downto 0);

io_buf: process(A,Y,OE) begin
if (OE = '1') then
Y = A;
else
Y = 'Z';
end if;

B = Y;
end process io_buf;

io_buf is just a label which is optional. Even if you give it a label adding the label at the end is always optional.

A process is not a subroutine. The list of inputs are not like the inputs/outputs of a subroutine. They are always inputs that will cause the process to "run". In VHDL2008 you can replace that list with an asterisk. If you want something modular to be used in multiple places you can make it a procedure or an entity. A procedure IS a subroutine. An entity is a module that is instantiated (connected to the rest of the circuit through a port map, i.e. a wire list).

io_buf: procedure (
signal A : in std_logic_vector(7 downto 0);
signal B : out std_logic_vector(7 downto 0);
signal Y : inout std_logic_vector(7 downto 0);
signal OE : in std_logic ) is
begin
if (OE = '1') then
Y = A;
else
Y = 'Z';
end if;

B = Y;
end procedure io_buf;


The simplest way to do this is to just use concurrent statements (the simplest type of VHDL. You don't really need the B bus at all since it is just the Y bus from the outside. So the only assignment you need is to drive the output bus to a high-Z state when you aren't driving data.

Y <= 'Z' when (OE = '0') else A;

You can add this if it is more clear

B <= Y;

Sorry if this doesn't help you. I was bored and it was useful for me to review.

--

Rick C.

-+ Get 1,000 miles of free Supercharging
-+ Tesla referral code - https://ts.la/richard11209

Thanks for spending your time on this.
Yes, I know the two examples of the 74245 I posted are in VHDL and not in Verilog, anyway I think I can use both languages in my Quartus design.
Here is the logic diagram of my 74245 implementation (yes, I want to make this device in my CPLD design) :

http://www.mediafire.com/file/q8qspgz60nfpqum/IC74245.pdf/file

Here's the whole design, it's a simple circuit made of few TTLs gates (with a socket that plugs into the hosting hardware)

http://www.mediafire.com/file/arry2cio0l2g3aw/design.pdf/file

I don't know if you can duplicate a '245 device in a 20 pin CPLD. That will require 16 outputs and I don't think they make 20 CPLDs with 20 outputs.

Why can't you just use a 74LS245 device? They are still made. Mouser has them in stock for less than a dollar.

--

Rick C.

+- Get 1,000 miles of free Supercharging
+- Tesla referral code - https://ts.la/richard11209

I explained myself bad, sorry.I want to port into a CPLD the schematics I attached in which there is a 74245, not doing a CPLD version of the 74245.And yes, I have considered to use an external 74245 instead of implenting it in the Quartus CPLD design whereas all the remaining logics you can see in the attached schematics will be implemented in the CPLD.

I forgot.As CPLD I will use a +5V Altera EPM7128 (TQFP100) with 84 I/O and 128 macrocells.I already successfully used it in other my projects.

Ok, that is more clear. I will say the EPM7128 is very much overkill for this design, but that's ok. Better too large than too small. So the code I gave you should do the job here is an example that does the full in and out of the '245. One I/O is A and the other B as in your schematic.


signal DA, DB : std_logic_vector (7 downto 0);
signal s402_2H, s401_fi, other_ck, s601 : std_logic;
signal RD_n, s603, s602, wait_n, FF1, FF2 : std_logic;

DA <= 'Z' when (s602 or RD_n = '1') else DB;
DB <= 'Z' when (s602 or not RD_n = '1') else DA;

wait_n <= not 402_2H or s601;
s602 <= FF1 and FF2 or s601;
s603 <= s602 or not RD_n;

process (other_ck, 402_2H_n) begin
if (402_2H = '1') then
FF1 <= '1';
elsif (rising_edge(other_ck))
FF1 <= s401_fi;
end if;

if (falling_edge(other_ck))
FF2 <= FF1;
end if;
end process;

This is the logic as shown on the page. It still needs the entity boilerplate to define the I/Os for the device which are the signals on the 28 pin connector.

Can you tell me what the design does? The '245 device seems to simple connect pins on the 28 pin socket back to itself, either in one direction or the other. What plugs into the socket??? It would appear to be an MCU which makes little sense to tie 8 lines back to themselves. Or maybe you are trying to replace one of the higher complexity bus interface devices that aren't made anymore?

There are a couple of parts of the schematic that are troubling. One is the use of the PREset pin on the FF. PREset and CLR are asynchronous logic (combinational) and have very particular timing constraints which will be very different inside the CPLD and a TTL device. Without a thorough understanding of the design it is hard to know if this will work well. It is better to use the synchronous logic with separate combinational logic. That can only be done with detailed info on the intended operation of the device.

The same thing applies to the use of two inverters to create the enable on the '245 device. This is a logic noop which will only create an ill defined delay. This is hard to do in a CPLD since the tools will optimize it out. It has the same timing concerns as the PREset on the FF.

The more info you can provide, the more help you can get.

--

Rick C.

++ Get 1,000 miles of free Supercharging
++ Tesla referral code - https://ts.la/richard11209

You got closer The design is a replacement of a custom IC used on some arcade boards.I've succesfully done reverse-engineering of this (and many other) custom ICs but I used simple TTL gates to achieve the result.This one has few logics hence I was a able to keep the same dimensions of original part by using surface mounted TTLs.But I have other with very big circuit, that's why I want to practice with CPLD.As said, for now I can only translate my TTL schematics into Quartus block diagram, I know it's not the right way, the best would be to understand the behaviour of the design and then write HDL code for it.Anyway, I tried this too under Quartus schematics, it works but the hosting hardware (the arcade board) crashes or shows other issue which are probably related to wrong timings.Right now I'm translating into Quartus schematics the latest that I reverse-engineered but sadly I run out of I/O of the EPM7128, my design is too big for it and can fit into the CPLD regardless the fact that the design use also three 2k x 8-bit static RAMs and three 74245 that I excluded from design and put them externally.But this was not enough to save I/O of the EPM7128 Probably an FPGA is the best solution for this design also because you can simulate RAMs with it (I think it's not possible with CPLDs, at least memory of that size)

As for you code, I would gladly try it but, forgive my ignorancy, I don't know how to define the I/0 inside VHDL and Verilog.

 

[Rick C]

On Wednesday, April 29, 2020 at 4:50:09 PM UTC-4, bri...@gmail.com wrote:

On Wednesday, 29 April 2020 21:48:55 UTC+2, Rick C wrote:
On Wednesday, April 29, 2020 at 6:44:37 AM UTC-4, bri...@gmail.com wrote:
On Wednesday, 29 April 2020 12:42:05 UTC+2, bri...@gmail.com wrote:
On Wednesday, 29 April 2020 12:33:29 UTC+2, Rick C wrote:
On Wednesday, April 29, 2020 at 5:11:25 AM UTC-4, bri...@gmail.com wrote:
On Wednesday, 29 April 2020 06:43:32 UTC+2, Rick C wrote:
Just so you know. If the ascii art drawing looks like gibberish you need to view it in a mono-spaced font.

Here is some (untested) VHDL to implement the buffer you need for the outside world. I'm sitting here bored, so thought I'd do something useful.

-- A is an input from the FPGA/CPLD innards
-- B is output to the FPGA/CPLD innards,
-- Y is external bidir
-- OE is a high true output enable
signal A, B, Y std_logic_vector (7 downto 0);

io_buf: process(A,Y,OE) begin
if (OE = '1') then
Y = A;
else
Y = 'Z';
end if;

B = Y;
end process io_buf;

io_buf is just a label which is optional. Even if you give it a label adding the label at the end is always optional.

A process is not a subroutine. The list of inputs are not like the inputs/outputs of a subroutine. They are always inputs that will cause the process to "run". In VHDL2008 you can replace that list with an asterisk. If you want something modular to be used in multiple places you can make it a procedure or an entity. A procedure IS a subroutine. An entity is a module that is instantiated (connected to the rest of the circuit through a port map, i.e. a wire list).

io_buf: procedure (
signal A : in std_logic_vector(7 downto 0);
signal B : out std_logic_vector(7 downto 0);
signal Y : inout std_logic_vector(7 downto 0);
signal OE : in std_logic ) is
begin
if (OE = '1') then
Y = A;
else
Y = 'Z';
end if;

B = Y;
end procedure io_buf;


The simplest way to do this is to just use concurrent statements (the simplest type of VHDL. You don't really need the B bus at all since it is just the Y bus from the outside. So the only assignment you need is to drive the output bus to a high-Z state when you aren't driving data.

Y <= 'Z' when (OE = '0') else A;

You can add this if it is more clear

B <= Y;

Sorry if this doesn't help you. I was bored and it was useful for me to review.

--

Rick C.

-+ Get 1,000 miles of free Supercharging
-+ Tesla referral code - https://ts.la/richard11209

Thanks for spending your time on this.
Yes, I know the two examples of the 74245 I posted are in VHDL and not in Verilog, anyway I think I can use both languages in my Quartus design.
Here is the logic diagram of my 74245 implementation (yes, I want to make this device in my CPLD design) :

http://www.mediafire.com/file/q8qspgz60nfpqum/IC74245.pdf/file

Here's the whole design, it's a simple circuit made of few TTLs gates (with a socket that plugs into the hosting hardware)

http://www.mediafire.com/file/arry2cio0l2g3aw/design.pdf/file

I don't know if you can duplicate a '245 device in a 20 pin CPLD. That will require 16 outputs and I don't think they make 20 CPLDs with 20 outputs.

Why can't you just use a 74LS245 device? They are still made. Mouser has them in stock for less than a dollar.

--

Rick C.

+- Get 1,000 miles of free Supercharging
+- Tesla referral code - https://ts.la/richard11209

I explained myself bad, sorry.I want to port into a CPLD the schematics I attached in which there is a 74245, not doing a CPLD version of the 74245.And yes, I have considered to use an external 74245 instead of implenting it in the Quartus CPLD design whereas all the remaining logics you can see in the attached schematics will be implemented in the CPLD.

I forgot.As CPLD I will use a +5V Altera EPM7128 (TQFP100) with 84 I/O and 128 macrocells.I already successfully used it in other my projects.

Ok, that is more clear. I will say the EPM7128 is very much overkill for this design, but that's ok. Better too large than too small. So the code I gave you should do the job here is an example that does the full in and out of the '245. One I/O is A and the other B as in your schematic.


signal DA, DB : std_logic_vector (7 downto 0);
signal s402_2H, s401_fi, other_ck, s601 : std_logic;
signal RD_n, s603, s602, wait_n, FF1, FF2 : std_logic;

DA <= 'Z' when (s602 or RD_n = '1') else DB;
DB <= 'Z' when (s602 or not RD_n = '1') else DA;

wait_n <= not 402_2H or s601;
s602 <= FF1 and FF2 or s601;
s603 <= s602 or not RD_n;

process (other_ck, 402_2H_n) begin
if (402_2H = '1') then
FF1 <= '1';
elsif (rising_edge(other_ck))
FF1 <= s401_fi;
end if;

if (falling_edge(other_ck))
FF2 <= FF1;
end if;
end process;

This is the logic as shown on the page. It still needs the entity boilerplate to define the I/Os for the device which are the signals on the 28 pin connector.

Can you tell me what the design does? The '245 device seems to simple connect pins on the 28 pin socket back to itself, either in one direction or the other. What plugs into the socket??? It would appear to be an MCU which makes little sense to tie 8 lines back to themselves. Or maybe you are trying to replace one of the higher complexity bus interface devices that aren't made anymore?

There are a couple of parts of the schematic that are troubling. One is the use of the PREset pin on the FF. PREset and CLR are asynchronous logic (combinational) and have very particular timing constraints which will be very different inside the CPLD and a TTL device. Without a thorough understanding of the design it is hard to know if this will work well. It is better to use the synchronous logic with separate combinational logic. That can only be done with detailed info on the intended operation of the device.

The same thing applies to the use of two inverters to create the enable on the '245 device. This is a logic noop which will only create an ill defined delay. This is hard to do in a CPLD since the tools will optimize it out. It has the same timing concerns as the PREset on the FF.

The more info you can provide, the more help you can get.

--

Rick C.

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You got closer The design is a replacement of a custom IC used on some arcade boards.I've succesfully done reverse-engineering of this (and many other) custom ICs but I used simple TTL gates to achieve the result.This one has few logics hence I was a able to keep the same dimensions of original part by using surface mounted TTLs.But I have other with very big circuit, that's why I want to practice with CPLD.As said, for now I can only translate my TTL schematics into Quartus block diagram, I know it's not the right way, the best would be to understand the behaviour of the design and then write HDL code for it.Anyway, I tried this too under Quartus schematics, it works but the hosting hardware (the arcade board) crashes or shows other issue which are probably related to wrong timings.Right now I'm translating into Quartus schematics the latest that I reverse-engineered but sadly I run out of I/O of the EPM7128, my design is too big for it and can fit into the CPLD regardless the fact that the design use also three 2k x 8-bit static RAMs and three 74245 that I excluded from design and put them externally.But this was not enough to save I/O of the EPM7128 Probably an FPGA is the best solution for this design also because you can simulate RAMs with it (I think it's not possible with CPLDs, at least memory of that size)

As for you code, I would gladly try it but, forgive my ignorancy, I don't know how to define the I/0 inside VHDL and Verilog.

You are obviously a very resourceful guy. You remind me of someone I worked with. He was hired by the head guy while working at a hotel restaurant, washing dishes I believe. He spoke poor English so didn't communicate well with the others. They put him on the test floor and within a few months was cranking out machines as fast as anyone. He was amazingly tenacious and took extensive notes.

I think you should take the step to using FPGAs and learning an HDL. I know VHDL and can teach you that, but many say it is harder to learn than Verilog. I don't know Verily nearly as well so can't guide you as well.

A recommended FPGA would be one of the Lattice devices. They can be bought in 100 pin QFP, well one part actually, but there are other packages you might like. 36, 48 and 72 pin QFN packages are common. The MachXO3D-4300 has everything you might want I think and comes in the QFN72 package. Internal flash so no external memory needed. 3.3 volt only power.

Lattice has free software to use with these parts.

--

Rick C.

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[Rick C]

With the entity declaration added the VHDL code becomes

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity Thing is
port (
DA, DB : inout std_logic_vector (7 downto 0);
s402_2H, s401_fi, other_ck, s601, RD_n : in std_logic;
s603, s602, wait_n : out std_logic
);
end Thing ;

architecture V1 of Thing is
signal FF1, FF2, OE : std_logic;
begin

DA <= 'Z' when ((OE and not RD_n) = '0') else DB;
DB <= 'Z' when ((OE and RD_n) = '0') else DA;

wait_n <= not 402_2H or s601;
s602 <= FF1 and FF2 or s601;
s603 <= s602 or not RD_n;
OE <= FF1 and FF2 and not s601;

process (other_ck, 402_2H_n) begin
if (402_2H = '1') then
FF1 <= '1';
elsif (rising_edge(other_ck)) then
FF1 <= s401_fi;
end if;

if (falling_edge(other_ck)) then
FF2 <= FF1;
end if;
end process;
end V1;

I don't have a track record of getting things right the first time. I don't see any issues with this code but that may not mean much, lol.

You can simulate the design on the computer if you know what the waveforms at IC1 should be. I assume you have a working device you can scope? If you can capture a few waveforms showing the typical cycles of operation I can generate a test bench that will simulate the design.

The signal to the enable pin on the '245 chip (G) is driven through two inverters most likely for the delay. I assume this is to allow what ever is driving the bus from the other side to turn off from the 602 signal so they aren't fighting. I created separate logic to enable the buffer from the 602 signal, but it is hard to add delays. It can be done by adding an attribute to an intermediate wire, but even then delays in CPLDs and FPGAs are partly due to routing. CPLDs have fewer routing options so less variation. Still, it may be hard to get the timing right, especially if you don't know what it needs to be.

--

Rick C.

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--+ Tesla referral code - https://ts.la/richard11209

 

[Caius]

On Thursday, 30 April 2020 08:19:09 UTC+2, Rick C wrote:

With the entity declaration added the VHDL code becomes

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity Thing is
port (
DA, DB : inout std_logic_vector (7 downto 0);
s402_2H, s401_fi, other_ck, s601, RD_n : in std_logic;
s603, s602, wait_n : out std_logic
);
end Thing ;

architecture V1 of Thing is
signal FF1, FF2, OE : std_logic;
begin

DA <= 'Z' when ((OE and not RD_n) = '0') else DB;
DB <= 'Z' when ((OE and RD_n) = '0') else DA;

wait_n <= not 402_2H or s601;
s602 <= FF1 and FF2 or s601;
s603 <= s602 or not RD_n;
OE <= FF1 and FF2 and not s601;

process (other_ck, 402_2H_n) begin
if (402_2H = '1') then
FF1 <= '1';
elsif (rising_edge(other_ck)) then
FF1 <= s401_fi;
end if;

if (falling_edge(other_ck)) then
FF2 <= FF1;
end if;
end process;
end V1;

I don't have a track record of getting things right the first time. I don't see any issues with this code but that may not mean much, lol.

You can simulate the design on the computer if you know what the waveforms at IC1 should be. I assume you have a working device you can scope? If you can capture a few waveforms showing the typical cycles of operation I can generate a test bench that will simulate the design.

The signal to the enable pin on the '245 chip (G) is driven through two inverters most likely for the delay. I assume this is to allow what ever is driving the bus from the other side to turn off from the 602 signal so they aren't fighting. I created separate logic to enable the buffer from the 602 signal, but it is hard to add delays. It can be done by adding an attribute to an intermediate wire, but even then delays in CPLDs and FPGAs are partly due to routing. CPLDs have fewer routing options so less variation. Still, it may be hard to get the timing right, especially if you don't know what it needs to be.

--

Rick C.

--+ Get 1,000 miles of free Supercharging
--+ Tesla referral code - https://ts.la/richard11209

Thanks for your words, I only hope to not end up washing dishes ahahaha
Anyway I tried to compile your code but unsuccessfully because Quartus complains about wrong syntax :

Error (10500): VHDL syntax error at thing.vhd(20) near text "or"; expecting ";"
Error (10500): VHDL syntax error at thing.vhd(24) near text "4022"; expecting an identifier, or a string literal

I can provide you signal analyzing with my digital oscilloscope (I guess of the outputs and clock signals or the whole bus syncronized with other signals?).

As for FPGA practicing I spotted this cheap dev board to play with :

http://land-boards.com/blwiki/index.php?title=Cyclone_II_EP2C5_Mini_Dev_Board

 

[Johann Klammer]

On 04/28/2020 08:24 PM, briccus@gmail.com wrote:

Hi all,
I'm new to Verilog (although I've been designing and repairing electronics since many years).Not being yet familiar with coding I'm porting to Quartus schematics block some designs of mine using the examples (primitives) in the library.There are a couple of designs with bidirectional bus (made by the 74LS245 transceiver) hence I was wondering how to accomplish this in Verilog.Here are snippets of schematics:

https://i.postimg.cc/HLDFnmFZ/bidir.jpg

https://i.postimg.cc/XvfMVrs7/bidir-2.jpg

Any help or suggestion is appreciated.Thanks in advance.

For gate level modelling the bufif0/1 and notif0/1 primitives exist.