Best way to reject 50Hz or 60Hz mains with ADS1118

P

Peter

Guest
The device offers the following sampling rates on the delta-sigma ADC:

8 16 32 64 128 250 475 860

The 16/sec conversion rate would alone reject 60Hz fairly accurately,
but there is no similar option for 50Hz.

Sampling at the highest speed (860/sec) and accumulating 14 or 17
readings respectively (and then dividing the total by the number of
samples), would do it, but then we don't get the natural noise
rejection of the slow ADC reading rates.

It seems that the best compromise is:
For 60Hz rejection, use the 16/sec reading rate directly. The
averaging feature is still available but is not necessary for 60Hz
rejection.
For 50Hz rejection, use the 250/sec reading rate and average last 5
readings.

However, I can't get my head around whether the 50Hz option will
really work.

It would obviously work if one added up 5 readings and divided it by 5
- a process which would take 20ms and that would be exact. Then you
start with a freshly initialised accumulator for the next 5. So the
system would deliver one reading every 20ms, only.

But will running (what I think is called) a FIR filter, with the last
5 readings held in a FIFO queue, have the same 50Hz rejection effect?
That delivers readings every 4ms.

I think it will work because the queue will contain 20ms' worth of
readings.

Many thanks for any insight. It's quite a subtle question!
 
On 2019-10-28 12:26, Peter wrote:
The device offers the following sampling rates on the delta-sigma ADC:

8 16 32 64 128 250 475 860

The 16/sec conversion rate would alone reject 60Hz fairly accurately,
but there is no similar option for 50Hz.

Sampling at the highest speed (860/sec) and accumulating 14 or 17
readings respectively (and then dividing the total by the number of
samples), would do it, but then we don't get the natural noise
rejection of the slow ADC reading rates.

It seems that the best compromise is:
For 60Hz rejection, use the 16/sec reading rate directly. The
averaging feature is still available but is not necessary for 60Hz
rejection.
For 50Hz rejection, use the 250/sec reading rate and average last 5
readings.

However, I can't get my head around whether the 50Hz option will
really work.

It would obviously work if one added up 5 readings and divided it by 5
- a process which would take 20ms and that would be exact. Then you
start with a freshly initialised accumulator for the next 5. So the
system would deliver one reading every 20ms, only.

But will running (what I think is called) a FIR filter, with the last
5 readings held in a FIFO queue, have the same 50Hz rejection effect?
That delivers readings every 4ms.
Click to expand...

Yes. It doesn't matter where in the cycle you start--it just matters
that you stop exactly a whole number of cycles later.

I think it will work because the queue will contain 20ms' worth of
readings.

Many thanks for any insight. It's quite a subtle question!
Click to expand...

Can you dork the clock rate?

Cheers

Phil Hobbs


--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC / Hobbs ElectroOptics
Optics, Electro-optics, Photonics, Analog Electronics
Briarcliff Manor NY 10510

http://electrooptical.net
http://hobbs-eo.com
 
On 28.10.19 18:26, Peter wrote:
The device offers the following sampling rates on the delta-sigma ADC:

8 16 32 64 128 250 475 860

The 16/sec conversion rate would alone reject 60Hz fairly accurately,
but there is no similar option for 50Hz.

Sampling at the highest speed (860/sec) and accumulating 14 or 17
readings respectively (and then dividing the total by the number of
samples), would do it, but then we don't get the natural noise
rejection of the slow ADC reading rates.

It seems that the best compromise is:
For 60Hz rejection, use the 16/sec reading rate directly. The
averaging feature is still available but is not necessary for 60Hz
rejection.
For 50Hz rejection, use the 250/sec reading rate and average last 5
readings.

However, I can't get my head around whether the 50Hz option will
really work.

It would obviously work if one added up 5 readings and divided it by 5
- a process which would take 20ms and that would be exact. Then you
start with a freshly initialised accumulator for the next 5. So the
system would deliver one reading every 20ms, only.

But will running (what I think is called) a FIR filter, with the last
5 readings held in a FIFO queue, have the same 50Hz rejection effect?
That delivers readings every 4ms.

I think it will work because the queue will contain 20ms' worth of
readings.

Many thanks for any insight. It's quite a subtle question!
Click to expand...

You'd better to keep the 50 or 60 Hz out of the inputs. The data
sheet is extremely careful to not specify any tolerance for the
internal oscillator frequency, and the filter nulls are pretty steep.

--

-TV
 
On 28/10/2019 16:26, Peter wrote:
The device offers the following sampling rates on the delta-sigma ADC:

8 16 32 64 128 250 475 860

The 16/sec conversion rate would alone reject 60Hz fairly accurately,
but there is no similar option for 50Hz.

Sampling at the highest speed (860/sec) and accumulating 14 or 17
readings respectively (and then dividing the total by the number of
samples), would do it, but then we don't get the natural noise
rejection of the slow ADC reading rates.

It seems that the best compromise is:
For 60Hz rejection, use the 16/sec reading rate directly. The
averaging feature is still available but is not necessary for 60Hz
rejection.
For 50Hz rejection, use the 250/sec reading rate and average last 5
readings.

However, I can't get my head around whether the 50Hz option will
really work.

It would obviously work if one added up 5 readings and divided it by 5
- a process which would take 20ms and that would be exact. Then you
start with a freshly initialised accumulator for the next 5. So the
system would deliver one reading every 20ms, only.

But will running (what I think is called) a FIR filter, with the last
5 readings held in a FIFO queue, have the same 50Hz rejection effect?
That delivers readings every 4ms.
Click to expand...

Although it does give a new reading every 4ms they are statistically
correlated to previous readings until the buffer contains entirely fresh
raw data so you really have only one new independent measurement every
20ms. The cancellation scheme works so long as you choose a measurement
averaging period that is an exact multiple of the mains period.

The first common one for 60Hz and 50Hz is 10Hz or 100ms of averaging.

I think it will work because the queue will contain 20ms' worth of
readings.

Many thanks for any insight. It's quite a subtle question!
Click to expand...

It depends how often you need samples which is the best tactic for
minimising mains interference when digitising weak signals.

-
Regards,
Martin Brown
 
On a sunny day (Mon, 28 Oct 2019 16:26:24 +0000) it happened Peter
<nospam@nospam9876.com> wrote in <qp74ri$d3d$1@dont-email.me>:

The device offers the following sampling rates on the delta-sigma ADC:

8 16 32 64 128 250 475 860

The 16/sec conversion rate would alone reject 60Hz fairly accurately,
but there is no similar option for 50Hz.
Click to expand...

Filtering BEFORE sampling is the way to go.
 
On a sunny day (Tue, 29 Oct 2019 10:47:18 +0000) it happened Martin Brown
<'''newspam'''@nezumi.demon.co.uk> wrote in <qp95bl$14vi$1@gioia.aioe.org>:

On 29/10/2019 09:04, Jan Panteltje wrote:
On a sunny day (Mon, 28 Oct 2019 16:26:24 +0000) it happened Peter
nospam@nospam9876.com> wrote in <qp74ri$d3d$1@dont-email.me>:

The device offers the following sampling rates on the delta-sigma ADC:

8 16 32 64 128 250 475 860

The 16/sec conversion rate would alone reject 60Hz fairly accurately,
but there is no similar option for 50Hz.

Filtering BEFORE sampling is the way to go.

Preventing interference pickup is always worthwhile but when you are
looking for the ultimate performance you have to accept that apart from
out in a field far away from any mains wiring there is always going to
be some small amount of mains noise magnetically coupled to your kit.

Solartron 7060 DVMs used to have swappable crystals so that their
sampling time could be made mains synchronous on all ranges.
Click to expand...

I already wrote that, but decided not to post it as it does possibly not 100 % apply for this case
but in general:
Suppose you sample at _exactly_ the mains frequency
and you take 1 sample at the time (every 20 mS where we live).
If you sample at the moment of that very common repetitive spike
then you consistently get the value of that spike...

Better is then to have some frequency difference and do signal processing after digitizing.
Filtering mains _and_ its harmonics before digitizing is much better
eliptical filter:
http://panteltje.com/panteltje/newsflex/download.html#humfilter
top link.

Spikes are always a problem, wide spectrum ...
but I gues everybody knows that..
Mains is NOT clean.
 
On 29/10/2019 09:04, Jan Panteltje wrote:
On a sunny day (Mon, 28 Oct 2019 16:26:24 +0000) it happened Peter
nospam@nospam9876.com> wrote in <qp74ri$d3d$1@dont-email.me>:

The device offers the following sampling rates on the delta-sigma ADC:

8 16 32 64 128 250 475 860

The 16/sec conversion rate would alone reject 60Hz fairly accurately,
but there is no similar option for 50Hz.

Filtering BEFORE sampling is the way to go.
Click to expand...

Preventing interference pickup is always worthwhile but when you are
looking for the ultimate performance you have to accept that apart from
out in a field far away from any mains wiring there is always going to
be some small amount of mains noise magnetically coupled to your kit.

Solartron 7060 DVMs used to have swappable crystals so that their
sampling time could be made mains synchronous on all ranges.

--
Regards,
Martin Brown
 
On 29/10/2019 11:08, Jan Panteltje wrote:
On a sunny day (Tue, 29 Oct 2019 10:47:18 +0000) it happened Martin Brown
'''newspam'''@nezumi.demon.co.uk> wrote in <qp95bl$14vi$1@gioia.aioe.org>:

On 29/10/2019 09:04, Jan Panteltje wrote:
On a sunny day (Mon, 28 Oct 2019 16:26:24 +0000) it happened Peter
nospam@nospam9876.com> wrote in <qp74ri$d3d$1@dont-email.me>:

The device offers the following sampling rates on the delta-sigma ADC:

8 16 32 64 128 250 475 860

The 16/sec conversion rate would alone reject 60Hz fairly accurately,
but there is no similar option for 50Hz.

Filtering BEFORE sampling is the way to go.

Preventing interference pickup is always worthwhile but when you are
looking for the ultimate performance you have to accept that apart from
out in a field far away from any mains wiring there is always going to
be some small amount of mains noise magnetically coupled to your kit.

Solartron 7060 DVMs used to have swappable crystals so that their
sampling time could be made mains synchronous on all ranges.

I already wrote that, but decided not to post it as it does possibly not 100 % apply for this case
but in general:
Suppose you sample at _exactly_ the mains frequency
and you take 1 sample at the time (every 20 mS where we live).
If you sample at the moment of that very common repetitive spike
then you consistently get the value of that spike...
Click to expand...

But these DACs are typically integrators over a period rather than flash
DAC converters of the instantaneous voltage so averaging over the mains
cycle period works pretty well to eliminate it. You might get an unlucky
reading every now and then as local crystal 50Hz beats against mains.
Better is then to have some frequency difference and do signal processing after digitizing.
Filtering mains _and_ its harmonics before digitizing is much better
eliptical filter:
http://panteltje.com/panteltje/newsflex/download.html#humfilter
top link.

Spikes are always a problem, wide spectrum ...
but I gues everybody knows that..
Mains is NOT clean.
Click to expand...

It never was but it is made worse by cheap and nasty SMPS.

--
Regards,
Martin Brown
 
On a sunny day (Tue, 29 Oct 2019 16:50:57 +0000) it happened Martin Brown
<'''newspam'''@nezumi.demon.co.uk> wrote in <qp9qlg$bim$1@gioia.aioe.org>:

But these DACs are typically integrators over a period rather than flash
DAC converters of the instantaneous voltage so averaging over the mains
Click to expand...

ADCs
DAC stands for Digital To Analog
 
On 29/10/2019 04:10, Phil Hobbs wrote:
On 2019-10-28 12:26, Peter wrote:
The device offers the following sampling rates on the delta-sigma ADC:

8 16 32 64 128 250 475 860

The 16/sec conversion rate would alone reject 60Hz fairly accurately,
but there is no similar option for 50Hz.

Sampling at the highest speed (860/sec) and accumulating 14 or 17
readings respectively (and then dividing the total by the number of
samples), would do it, but then we don't get the natural noise
rejection of the slow ADC reading rates.

It seems that the best compromise is:
For 60Hz rejection, use the 16/sec reading rate directly. The
averaging feature is still available but is not necessary for 60Hz
rejection.
For 50Hz rejection, use the 250/sec reading rate and average last 5
readings.

However, I can't get my head around whether the 50Hz option will
really work.

It would obviously work if one added up 5 readings and divided it by 5
- a process which would take 20ms and that would be exact. Then you
start with a freshly initialised accumulator for the next 5. So the
system would deliver one reading every 20ms, only.

But will running (what I think is called) a FIR filter, with the last
5 readings held in a FIFO queue, have the same 50Hz rejection effect?
That delivers readings every 4ms.

Yes.  It doesn't matter where in the cycle you start--it just matters
that you stop exactly a whole number of cycles later.
Click to expand...

[to the OP]
But of course to achieve good rejection at 50Hz, the
weights/coefficients of the FIR filter need to be chosen properly (e.g.
one tap 1 and the rest zero is obviously no good).

For example, all coefficients the same, i.e. a running average would
work, or two equal non-zero coefficients for taps exactly 10ms apart and
the rest of the coefficients zero would work, etc. The best choice of
coefficients might depend on whether rejection of other frequencies
(such as harmonics) is desired, and what step response you need. This is
all fairly straightforward to simulate, e.g. in Octave or Matlab.
 
On 30/10/2019 08:43, Jan Panteltje wrote:
On a sunny day (Tue, 29 Oct 2019 16:50:57 +0000) it happened Martin Brown
'''newspam'''@nezumi.demon.co.uk> wrote in <qp9qlg$bim$1@gioia.aioe.org>:

But these DACs are typically integrators over a period rather than flash
DAC converters of the instantaneous voltage so averaging over the mains

ADCs
DAC stands for Digital To Analog

TYpoe
Click to expand...

--
Regards,
Martin Brown
 
Thank you for the most helpful replies.

Phil Hobbs <pcdhSpamMeSenseless@electrooptical.net> wrote:

But will running (what I think is called) a FIR filter, with the last
5 readings held in a FIFO queue, have the same 50Hz rejection effect?
That delivers readings every 4ms.

Yes. It doesn't matter where in the cycle you start--it just matters
that you stop exactly a whole number of cycles later.
Click to expand...

Great - thank you.

I think it will work because the queue will contain 20ms' worth of
readings.

Many thanks for any insight. It's quite a subtle question!


Can you dork the clock rate?
Click to expand...

Not on this chip. But yes that would have been an interesting tactic,
too.

I do have a lowpass filter on the input. It is 2.2uF ceramic and 2k2.
This is followed by a TLV2333 (chopper stabilised op-amp) voltage
follower, because the ADS1118 doesn't have a particularly high Zin. I
can't up the lowpass filter components much for various reasons.

To get a really good lowpass filter at 50Hz would take a lot of
components.
 
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