O
Oli
Guest
Hi,
Sorry for the long winded post, skip to the starred part for main
question
I am still getting up to speed with FPGAs and verilog - i.e. I can get
things to work, but probably not in an ideal fashion.
I have been tasked with development through to production stage so I
need to make sure my designs are efficient and most importantly,
reliable.
The problem I have currently - I have a design with multiple clock
domains on an Actel ProASIC3 250K gate:
One slow (~20MHz) soft core domain with SPI interface to external uC.
One high speed sample capture to RAM domain (~200MHz)
I have used double flopping for the one control signal that passes
between the domains, also the soft core reads the samples back after
capture has ceased (do I need to double flop these signals too?) and
basic capture works okay.
** The main issue is that I am reading 8 bits at 200MHz, so to make
things easier I thought I would use a 16 bit register/bus to halve the
clock speed for the following logic and RAM capture. It worked okay
using a derived clock (the 8 to 16 shift register logic also produces
the RAM address and clock) but I know this is not a good practice. I
also need to be able to vary the rate at which samples are loaded to
RAM and the address incremented, though I think this is less of a
problem.
So I would very much appreciate any advice on how to do this best. My
ideas from what I have read are:
Can I use the same clock and an enable tick for the 16-bit RAM logic
to avoid the derived clock?
Or apply constraints and declare the net as a clock so the synthesis
tool understands my intentions and uses the global clock resources for
the derived clock?
Any advice very much appreciated, most books I have read seem to be
quite clear on what is bad practice, but not many explain how to do
things best if you must use things like multiple clocks and
asynchronous parts to a design.
Sorry for the long winded post, skip to the starred part for main
question
I am still getting up to speed with FPGAs and verilog - i.e. I can get
things to work, but probably not in an ideal fashion.
I have been tasked with development through to production stage so I
need to make sure my designs are efficient and most importantly,
reliable.
The problem I have currently - I have a design with multiple clock
domains on an Actel ProASIC3 250K gate:
One slow (~20MHz) soft core domain with SPI interface to external uC.
One high speed sample capture to RAM domain (~200MHz)
I have used double flopping for the one control signal that passes
between the domains, also the soft core reads the samples back after
capture has ceased (do I need to double flop these signals too?) and
basic capture works okay.
** The main issue is that I am reading 8 bits at 200MHz, so to make
things easier I thought I would use a 16 bit register/bus to halve the
clock speed for the following logic and RAM capture. It worked okay
using a derived clock (the 8 to 16 shift register logic also produces
the RAM address and clock) but I know this is not a good practice. I
also need to be able to vary the rate at which samples are loaded to
RAM and the address incremented, though I think this is less of a
problem.
So I would very much appreciate any advice on how to do this best. My
ideas from what I have read are:
Can I use the same clock and an enable tick for the 16-bit RAM logic
to avoid the derived clock?
Or apply constraints and declare the net as a clock so the synthesis
tool understands my intentions and uses the global clock resources for
the derived clock?
Any advice very much appreciated, most books I have read seem to be
quite clear on what is bad practice, but not many explain how to do
things best if you must use things like multiple clocks and
asynchronous parts to a design.