best way to do this continuous assignment

I have a two wires:
wire [m-1:0] wire1;
wire [n*m-1:0] wire2;

and I want connect wire1 to wire2 but replicate each bit of wire1
(0..m-1), n times.

m and n are parameters so I don't want to do it explicitly i.e. a
separate assign for each value of m because this would not be re-
usable.

e.g. for m=5, n=3
wire1 value = 10111
wire2 value = 111000111111111

is this possible? Thanks.

 

[John_H]

<David.Wooff@gmail.com> wrote in message
news:1174500048.086225.77540@p15g2000hsd.googlegroups.com...

I have a two wires:
wire [m-1:0] wire1;
wire [n*m-1:0] wire2;

and I want connect wire1 to wire2 but replicate each bit of wire1
(0..m-1), n times.

m and n are parameters so I don't want to do it explicitly i.e. a
separate assign for each value of m because this would not be re-
usable.

e.g. for m=5, n=3
wire1 value = 10111
wire2 value = 111000111111111

is this possible? Thanks.

The generate blocks are great for this sort of thing if you're using
Verilog2001 compliant tools. You end up generating n*m assignments in two
for loops.

Without the generate to provide the continuous assignments, you could use an
"always @*" style block to get the combinatorial results using normal for
loops.

 

On Mar 21, 6:33 pm, "John_H" <newsgr...@johnhandwork.com> wrote:

David.Wo...@gmail.com> wrote in message

news:1174500048.086225.77540@p15g2000hsd.googlegroups.com...



I have a two wires:
wire [m-1:0] wire1;
wire [n*m-1:0] wire2;

and I want connect wire1 to wire2 but replicate each bit of wire1
(0..m-1), n times.

m and n are parameters so I don't want to do it explicitly i.e. a
separate assign for each value of m because this would not be re-
usable.

e.g. for m=5, n=3
wire1 value = 10111
wire2 value = 111000111111111

is this possible? Thanks.

The generate blocks are great for this sort of thing if you're using
Verilog2001 compliant tools. You end up generating n*m assignments in two
for loops.

Without the generate to provide the continuous assignments, you could use an
"always @*" style block to get the combinatorial results using normal for
loops.

So, can I make a continuous assignment inside a generate for-loop?
I'll try this tomorrow.
Thanks very much.

 

[nezhate]

On Mar 22, 1:27 am, David.Wo...@gmail.com wrote:

On Mar 21, 6:33 pm, "John_H" <newsgr...@johnhandwork.com> wrote:



David.Wo...@gmail.com> wrote in message

news:1174500048.086225.77540@p15g2000hsd.googlegroups.com...

I have a two wires:
wire [m-1:0] wire1;
wire [n*m-1:0] wire2;

and I want connect wire1 to wire2 but replicate each bit of wire1
(0..m-1), n times.

m and n are parameters so I don't want to do it explicitly i.e. a
separate assign for each value of m because this would not be re-
usable.

e.g. for m=5, n=3
wire1 value = 10111
wire2 value = 111000111111111

is this possible? Thanks.

The generate blocks are great for this sort of thing if you're using
Verilog2001 compliant tools. You end up generating n*m assignments in two
for loops.

Without the generate to provide the continuous assignments, you could use an
"always @*" style block to get the combinatorial results using normal for
loops.

So, can I make a continuous assignment inside a generate for-loop?
I'll try this tomorrow.
Thanks very much.

Of course it will work.... in the past I've got one design that was
maded only from genrate blocks within multiple assignements.