Best way to address block ram?

I have block ram that will contain 50,000 objects. Gonna use a decoder
of some sort to be able to retrieve the data. Used a case statement at
first but that would be huge with 50,000 if statements in it. Thought
about using a hash table but that would be big too. Whats the most
effeicient way to accomplish this?

 

You did not mention if this is for a synhesizabe design or a testbench.

Is there a way to break the information that you are trying to decode
into multiple groupings so as to simplify the decoding? Thus, the
storing of the data is stored at certain addresses based on content of
the data. Perhaps you can be more explicit about your requirements.
--------------------------------------------------------------------------
Ben Cohen Trainer, Consultant, Publisher (831) 345-1759
http://www.abv-sva.org/ ben@abv-sva.org
* Training for VMM, SVA and PSL
* Co-Author: SystemVerilog Assertions Handbook, 2005 ISBN 0-9705394-7-9
* Co-Author: Using PSL/SUGAR for Formal and Dynamic Verification 2nd
Edition, 2004, ISBN 0-9705394-6-0
* Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn
0-9705394-2-8
* Component Design by Example ", 2001 isbn 0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn
0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn
0-7923-8115
---------------------------------------------------------------------------

 

This is for a synthesizable design. The way the data is stored in the
memory is theres are 50 objects in a row and there are 1000 rows. So
the length of the row and columns are known but im not sure how to
manipulate that into something useful.

hdlcohen@gmail.com wrote:

You did not mention if this is for a synhesizabe design or a testbench.

Is there a way to break the information that you are trying to decode
into multiple groupings so as to simplify the decoding? Thus, the
storing of the data is stored at certain addresses based on content of
the data. Perhaps you can be more explicit about your requirements.
--------------------------------------------------------------------------
Ben Cohen Trainer, Consultant, Publisher (831) 345-1759
http://www.abv-sva.org/ ben@abv-sva.org
* Training for VMM, SVA and PSL
* Co-Author: SystemVerilog Assertions Handbook, 2005 ISBN 0-9705394-7-9
* Co-Author: Using PSL/SUGAR for Formal and Dynamic Verification 2nd
Edition, 2004, ISBN 0-9705394-6-0
* Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn
0-9705394-2-8
* Component Design by Example ", 2001 isbn 0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn
0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn
0-7923-8115
---------------------------------------------------------------------------

 

You could consider a microcode approach where you use a ROM as a
decoder.
Thus, for 50 objects in a row and 1000 rows, you would need a 50KByte
or 50KWord ROM, where each byte or word helps in the decode. This is
very fast. You'll have to architect the configuration and thecoding of
this ROM. This is a standard microcode programming effort.
Ben
dhbrewer@gmail.com wrote:

This is for a synthesizable design. The way the data is stored in the
memory is theres are 50 objects in a row and there are 1000 rows. So
the length of the row and columns are known but im not sure how to
manipulate that into something useful.

hdlcohen@gmail.com wrote:
You did not mention if this is for a synhesizabe design or a testbench.

Is there a way to break the information that you are trying to decode
into multiple groupings so as to simplify the decoding? Thus, the
storing of the data is stored at certain addresses based on content of
the data. Perhaps you can be more explicit about your requirements.
--------------------------------------------------------------------------
Ben Cohen Trainer, Consultant, Publisher (831) 345-1759
http://www.abv-sva.org/ ben@abv-sva.org
* Training for VMM, SVA and PSL
* Co-Author: SystemVerilog Assertions Handbook, 2005 ISBN 0-9705394-7-9
* Co-Author: Using PSL/SUGAR for Formal and Dynamic Verification 2nd
Edition, 2004, ISBN 0-9705394-6-0
* Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn
0-9705394-2-8
* Component Design by Example ", 2001 isbn 0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn
0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn
0-7923-8115
---------------------------------------------------------------------------