Being refused for an evaluation license of Questa

G

goannae

Guest
because I am a lowly PhD student ;(

Never touch anything to do with that company again!

Could you suggest any alternatives, I would like to learn SV?
 
"goannae" <jihan.zhu@gmail.com> wrote in message
news:1174482068.862239.125070@e1g2000hsg.googlegroups.com...
because I am a lowly PhD student ;(

Never touch anything to do with that company again!

Could you suggest any alternatives, I would like to learn SV?
Click to expand...
Do you live in the 1990s? At that time there was no freeware and had to
learn
Verilog/VHDL in big organizations.

Nowadays many Verilog software are free.

You can download ModelSim for Xilinx or Altera, which are free.
And you can use Xilinx ISE to synthesize your codes, up to pretty large
designs.
 
On Mar 21, 1:01 pm, "goannae" <jihan....@gmail.com> wrote:
because I am a lowly PhD student ;(

Never touch anything to do with that company again!

Could you suggest any alternatives, I would like to learn SV?
Click to expand...
Mentor provides various means for students to legitimately access it's
products.

You can get ModelSim PE student edition as a free download from
http://www.model.com/resources/student_edition/student_default.asp

Which will give you basic VHDL or Verilog simulation capabilities (inc
SystemVerilog design constructs)


If you need access to the full ModelSim or Questa products (or other
tools), then our Higher Education Program (HEP) allows colleges and
universities to access to a broad range of Mentor's products for a
nominal fee.
http://www.mentor.com/company/higher_ed/index.cfm

I hope this helps

regards

- Nigel
 
Thank you. What is the best tool to learn systemverilog? Modelsim 6.2
does not support SV's "Class" constructs. This feature is only
supported in Questa along with a lot of assertion features. Our HEP
contract does not include questasim. It is really frustrating to find
a decent tool to learn systemverilog with.

Goa.


On Mar 22, 1:14 am, "NigelE" <nigel_ell...@mentor.com> wrote:
On Mar 21, 1:01 pm, "goannae" <jihan....@gmail.com> wrote:

because I am a lowly PhD student ;(

Never touch anything to do with that company again!

Could you suggest any alternatives, I would like to learn SV?

Mentor provides various means for students to legitimately access it's
products.

You can get ModelSim PE student edition as a free download fromhttp://www.model.com/resources/student_edition/student_default.asp

Which will give you basic VHDL or Verilog simulation capabilities (inc
SystemVerilog design constructs)

If you need access to the full ModelSim or Questa products (or other
tools), then our Higher Education Program (HEP) allows colleges and
universities to access to a broad range of Mentor's products for a
nominal fee.http://www.mentor.com/company/higher_ed/index.cfm

I hope this helps

regards

- Nigel
Click to expand...
 
"goannae" <jihan.zhu@gmail.com> wrote in message
news:1174528230.879971.309920@y80g2000hsf.googlegroups.com...
Thank you. What is the best tool to learn systemverilog? Modelsim 6.2
does not support SV's "Class" constructs. This feature is only
supported in Questa along with a lot of assertion features. Our HEP
contract does not include questasim. It is really frustrating to find
a decent tool to learn systemverilog with.
Click to expand...
There are no free/low-cost complete Systemverilog 3.1a simulators yet.
Modelsim XE-III Starter (from xilinx.com) and Modelsim PE Student (from
mentor.com)
are your only choices. And you already know neither product will
do 'verification' features (classes, assertions, coverage, programs,
clocking-blocks, etc.)

The only thing I can say is you'll have to ask your profsesor/advisor
if he can get more funding, to purchase Questa under the HEP contract.
That is the least expensive way to get a cheaper SV31a tool.
 
On Mar 22, 2:50 am, "goannae" <jihan....@gmail.com> wrote:
Thank you. What is the best tool to learn systemverilog? Modelsim 6.2
does not support SV's "Class" constructs. This feature is only
supported in Questa along with a lot of assertion features. Our HEP
contract does not include questasim. It is really frustrating to find
a decent tool to learn systemverilog with.
Click to expand...
It sounds like the books are further than the tools. The question is
whether your emphasis is on the SystemVerilog part or an object
oriented based verification approach. If you are interested in the
later, maybe the C++ based approach teal/truss is an idea: http://trusster.com/

Cheers,

Guenter
 
Hi Goa,

I have forwarded your e-mail to some people at Mentor. I will do my
best to help get you a questa eval license. My e-mail is mike at
trusster .

Guenter, thanks for the plug! Yes, the books are ahead of the
language. The language is also immature. Robert and I will have a
SystemVerilog vesion of our C++ book due out at DAC. This book will
stick to the OOP features of System Verilog that are implemented by
Mentor and Synopsys. This is also the case with our open source
framework.

Robert and I feel strongly that OOP is the way to go for verification,
independent of the language one chooses.

Take Care,
Mike

On Mar 22, 2:00 pm, "Guenter" <GHEDWHCVE...@spammotel.com> wrote:
On Mar 22, 2:50 am, "goannae" <jihan....@gmail.com> wrote:

Thank you. What is the best tool to learn systemverilog? Modelsim 6.2
does not support SV's "Class" constructs. This feature is only
supported in Questa along with a lot of assertion features. Our HEP
contract does not include questasim. It is really frustrating to find
a decent tool to learn systemverilog with.

It sounds like the books are further than the tools. The question is
whether your emphasis is on the SystemVerilog part or an object
oriented based verification approach. If you are interested in the
later, maybe the C++ based approach teal/truss is an idea:http://trusster.com/

Cheers,

Guenter
Click to expand...
 
On Mar 21, 9:50 pm, "goannae" <jihan....@gmail.com> wrote:
Thank you. What is the best tool to learn systemverilog? Modelsim 6.2
does not support SV's "Class" constructs. This feature is only
supported in Questa along with a lot of assertion features. Our HEP
contract does not include questasim. It is really frustrating to find
a decent tool to learn systemverilog with.
Click to expand...
That's interesting... All this time, I assumed that ModelSim was an
inferior simulator to VCS because I could never get any of these
functions working!

A quick check of our academic licenses from Mentor reveals that we
don't have access to Questa either. It's quite a shame too because
I've been working with many design-oriented features of SV lately both
with ModelSim and Precision RTL.

----
Edmond Coté, Research Assistant
Computer Architecture Lab
Queen's University at Kingston
 
You must log in or register to reply here.

Welcome to EDABoard.com

Sponsor

Back
Top