Behavioural VHDL and Synthesis Tools

[Edmond Cote]

Hi,

I was wondering if anyone could point me towards some information on
the differences between synthesis tools and how they handle wait
statements within processes (w/o sensitivity lists).

I've been working recently with XST and I've found that its synthesis
rules are perhaps too constrained w/ regards to wait statements. As I am
still a student, I have access to a bunch of different tools and perhaps
it would be time to change for something more advanced (eg: Synopsys?)

The application of all this is currently to synthesize hardware on an
FPGA to perform a bus read/write cycle (which yes, could very well be
done at the RTL.. but if I could make it easier for myself I would)

Thanks in advance for your help,

Edmond