behavioural model

[galaticos]

Hello,

I have some very basic doubts reg. VHDL. As I am new to VHDL I am
unable to figure it out myself. Hope the Q's are appropriate!!

What do you exactly mean by behavioural model? U need not show the
boolean relation between the input n output right? My idea is that u
just need to describe the process going on inside each box. U need not
give the boolean expression for the ouput while writing the
architecture of the box. Is it correct?

Thanks,

galaticos

 

[Mike Treseler]

galaticos wrote:

What do you exactly mean by behavioural model?

I don't think it *exactly* means anything
so I don't use the term.

However, I do know that this question often
occurs when someone is reading the filler
in chapter one in a vhdl textbook

If you need a definition, combine one or more
of the following:

A behavioral model is a hardware description that

1. ... is not synthesizable, uses wait statements.

2. ... has no instances.

3. ... is synthesizable but needs more work
to reduce utilization or increase fmax

4. ... uses conditional statements instead
of boolean expressions.

etc., etc.

-- Mike Treseler

 

[Kunal]

I am new to VHDL myself. But I took a class where they said that the
behavioral model is the non-synthesizable version of your HDL, which
you use for initial simulations.