behavioural model

[galaticos]

Hello,

I have some very basic doubts reg. VHDL. As I am new to VHDL I am
unable to figure it out myself. Hope the Q's are appropriate!!

What do you exactly mean by behavioural model? U need not show the
boolean relation between the input n output right? My idea is that u
just need to describe the process going on inside each box. U need not
give the boolean expression for the ouput while writing the
architecture of the box. Is it correct?

Thanks,

galaticos

 

[Andy Peters]

galaticos wrote:

Hello,

I have some very basic doubts reg. VHDL. As I am new to VHDL I am
unable to figure it out myself. Hope the Q's are appropriate!!

What do you exactly mean by behavioural model? U (sic) need not show the
boolean relation between the input n output right? My idea is that u (sic)
just need to describe the process going on inside each box. U (sic) need not
give the boolean expression for the ouput while writing the
architecture of the box. Is it correct?

Basically, the terms mean whatever you want them to mean. One could
argue (and I like this argument) that the RTL description involves
low-level instances of specific flip-flops and gates, whereas a
behavioral description is at a higher level and describes the behavior
(sorry for the redundancy) of the design without getting into the nuts
and bolts of the exact implementation. Think of it as assembly code vs
C.

Some behavioral descriptions may not be synthesizable, but many are. A
common example of a synthesizable behavioral model is the basic
synchronous loadable, enable-able counter:

counter : process (clk, rst) is
begin
if (rst = '1') then
cnt <= 0;
elsif (rising_edge(clk)) then
if (load = '1') then
cnt <= INITVAL;
elsif (enable = '1') then
cnt <= (cnt + 1) mod ROLLOVER;
end if;
end if;
end process counter;

That's a clear, concise behavioral description of a counter that also
synthesizes. If you want the RTL, then synthesize it and tell the
tools to spit out a post-synthesis VHDL simulation model.

An example of an RTL model is the Xilinx Picoblaze processor. The
model is a bunch of instantiated flops, gates, shift registers and
memories. When you look at the code, your reaction may be, "well, I
assume this all works but I'm not gonna try to figure it out as I have
better things to do."

The point is, of course, that if you can describe the behavior of your
circuit at a high level, do so -- that's the point of hardware
DESCRIPTION languages, right? As long as the design is functionally
correct and meets timing, then the implementation is a detail you don't
have to worry about.

-a

 

[krby_xtrm]

behavioral model simply means that you model the design based on it's
BEHAVIOR.
and this kind of modelling is what makes vhdl very useful.

say if I INPUT something in this 'box' it will output something...
ex.
if input = 1 then output <= 100; -- something like that

behavioral models may or may not be synthesizable, it all depends on
the syntax...
one thing that is not synthesizable in design is code like this:

a <= b after 10ns;
-- this code generally describes that a gets b AFTER 10 nanosecond.

w/c only works on VHDL behavioral simulation models(non-synthesizable)

after all VHDL is a powerful Hardware Description Language
(synthesizable and non-synthesizable)