Behaviour of Xilinx FPGA pins during Slave Serial Download.

[A Beaujean]

I am trying to understand some very specifics of the behaviour of the
I/O pins of the Xilinx SpartanII family, that I went through in a not
quite clean prototype setup.

The situation was as follows:

I/O pins defined as future outputs,

I/O pins connected to a DSP control bus and an old FLUKE (Philips)
state analyzer, probably presenting an impedance of a few tens of
Kohms to ground per input,

Configuration mode = all '1' (Serial Slave Mode, no pre-configuration
pullups), 6 FPGA's in a row.

By mistake, no pullups or pulldowns on the pins. Thus, a situation
where, before programming, voltage on the pins is floating and
probably dictated by leakage currents and the equivalent impedance of
the state analyzer,

Before programming : all I/O's are seen as "HIGH" (Vcc) by the State
Analyzer (confirmed by scope reading),

BUT : when programming in Slave Serial Mode, somewhere during
programming, ALL I/O pins are pulled to "LOW", then return back to
"HIGH" at the end of the programming.

A reasonable explanation is that the DSP input leakage current, high
enough to keep the pins at Vcc when not in programming mode, is not
large enough during the programming and is "eaten" by some current
pumped to ground by the FPGA.

Adding a 10K pullup to 3V3 is enough to always keep the voltage on the
pins at "HIGH" during the programming.

Has anyone got an explanation for this behaviour ?

A. Beaujean