Oct 18, 2005 #1 Guest I have a very basic doubt in vhdl, what do you exactly mean by single entity-architecture pair? Haran
I have a very basic doubt in vhdl, what do you exactly mean by single entity-architecture pair? Haran
Oct 18, 2005 #2 M Mike Treseler Guest nkharan@gmail.com wrote: what do you exactly mean by single entity-architecture pair? Click to expand... http://groups.google.com/groups?q=vhdl+%22design+entity%22+interface
nkharan@gmail.com wrote: what do you exactly mean by single entity-architecture pair? Click to expand... http://groups.google.com/groups?q=vhdl+%22design+entity%22+interface
