Behavioral voltage source

A

ambi

Guest
Hi,
I am a bit new to cadence and I am trying to create a behavioral
voltage source like those available in some of the Spice tools.
I basically want to have a voltage source with output Vout=(V(VREFP)-
V(VREFM))/2 . where VREFP and VREFM are 2 distinct voltages.
In LTSpice which I am using currently, I can place a component called
behavioral voltage source on the schematic and mention its value as
V=(V(VREFP)-V(VREFM))/2.
Can anyone suggest how to get this in cadence ?
Thanks

Ambi
 
I found that there is something called bsource in Cadence ( "spectre -
h bsource" ) . If it is available as a component, I couldnt find it in
'analoglib' or 'ahdllib' . Can someone clarify this for me please.

Thanks
Ambi

On May 13, 2:23 am, ambi <radicalmah...@gmail.com> wrote:
Hi,
I am a bit new to cadence and I am trying to create a behavioral
voltage source like those available in some of the Spice tools.
I basically want to have a voltage source with output Vout=(V(VREFP)-
V(VREFM))/2 . where VREFP and VREFM are 2 distinct voltages.
In LTSpice which I am using currently, I can place a component called
behavioral voltage source on the schematic and mention its value as
V=(V(VREFP)-V(VREFM))/2.
Can anyone suggest how to get this in cadence ?
Thanks

Ambi
Click to expand...
 
On May 13, 3:23 am, ambi <radicalmah...@gmail.com> wrote:
Hi,
      I am a bit new to cadence and I am trying to create a behavioral
voltage source like those available in some of the Spice tools.
I basically want to have a voltage source with output Vout=(V(VREFP)-
V(VREFM))/2 . where VREFP and VREFM are 2 distinct voltages.
In LTSpice which I am using currently, I can place a component called
behavioral voltage source on the schematic and mention its value as
V=(V(VREFP)-V(VREFM))/2.
Can anyone suggest how to get this in cadence ?
Thanks

Ambi
Click to expand...
You can create the behavioral voltage source with the veriloga
behavioral language
(veriloga cell). Something like:

module myvsource(vrefp, vrefm, vout) ;
electrical vrefp,vrefm,vout ;
input vrefp, vrefm ;
output vout ;

analog begin
V(vout) <+ (V(vrefp)-V(vrefm))/2 ;
end
endmodule

Oliver
 
On May 13, 7:20 am, oliver <scr...@free.fr> wrote:
On May 13, 3:23 am, ambi <radicalmah...@gmail.com> wrote:

Hi,
I am a bit new to cadence and I am trying to create a behavioral
voltage source like those available in some of the Spice tools.
I basically want to have a voltage source with output Vout=(V(VREFP)-
V(VREFM))/2 . where VREFP and VREFM are 2 distinct voltages.
In LTSpice which I am using currently, I can place a component called
behavioral voltage source on the schematic and mention its value as
V=(V(VREFP)-V(VREFM))/2.
Can anyone suggest how to get this in cadence ?
Thanks

Ambi

You can create the behavioral voltage source with the veriloga
behavioral language
(veriloga cell). Something like:

module myvsource(vrefp, vrefm, vout) ;
electrical vrefp,vrefm,vout ;
input vrefp, vrefm ;
output vout ;

analog begin
V(vout) <+ (V(vrefp)-V(vrefm))/2 ;
end
endmodule

Oliver
Click to expand...
Thanks Oliver. But I am trying not to use verilog A. The design
constraint wants me to avoid using verologA. I need it as a component
to use it in my schematic.

Regards,
Ambi
 
ambi wrote, on 05/13/08 22:56:
On May 13, 7:20 am, oliver <scr...@free.fr> wrote:
On May 13, 3:23 am, ambi <radicalmah...@gmail.com> wrote:

Hi,
I am a bit new to cadence and I am trying to create a behavioral
voltage source like those available in some of the Spice tools.
I basically want to have a voltage source with output Vout=(V(VREFP)-
V(VREFM))/2 . where VREFP and VREFM are 2 distinct voltages.
In LTSpice which I am using currently, I can place a component called
behavioral voltage source on the schematic and mention its value as
V=(V(VREFP)-V(VREFM))/2.
Can anyone suggest how to get this in cadence ?
Thanks
Ambi
You can create the behavioral voltage source with the veriloga
behavioral language
(veriloga cell). Something like:

module myvsource(vrefp, vrefm, vout) ;
electrical vrefp,vrefm,vout ;
input vrefp, vrefm ;
output vout ;

analog begin
V(vout) <+ (V(vrefp)-V(vrefm))/2 ;
end
endmodule

Oliver

Thanks Oliver. But I am trying not to use verilog A. The design
constraint wants me to avoid using verologA. I need it as a component
to use it in my schematic.

Regards,
Ambi
Click to expand...
You can use bsource, as you suggested. However, the main reason it is not
supported from analogLib is that the expression would confuse the netlisting
process, and it would think that there are other design variables and so on which
are there.

So you'd have to include the component via an included netlist.

Alternatively, why not just use a vcvs with a gain of 0.5? That can easily be
placed on the schematic...

Andrew.
 
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