Beginner trying to do something simple...

[John Oyler]

I'm using xilinx's webpack software to try to synthesize. Most of my
stuff is syntactically correct, removing a few problem lines will let
it synth with no errors or warnings. However, one of the important
things I've still not figured out what to do.

I've declared two busses as inout, each 8 bits wide. I have my main
loop set for clk's posedge, and within that I have a case select
checking the value of data bus A. All is good so far. The problem
comes within the individual case statements... if A[7:0] is a certain
value (h00 and h20 come to mind), I want to output that same value
onto B[7:0].

If I simply put as my statement B[7:0] <= A[7:0] or if I do B[7:0] =
A[7:0] it freaks out, with 2 errors per instance of such statements.
Am I declaring these wrong? Is there something more involved? If more
is needed, I'll post the errors themselves tomorrow morning, but I
figure I'm doing something boneheaded enough that even with this much,
it should be obvious.

Any and all help appreciated.

 

[John_H]

John Oyler wrote:

I'm using xilinx's webpack software to try to synthesize. Most of my
stuff is syntactically correct, removing a few problem lines will let
it synth with no errors or warnings. However, one of the important
things I've still not figured out what to do.

I've declared two busses as inout, each 8 bits wide. I have my main
loop set for clk's posedge, and within that I have a case select
checking the value of data bus A. All is good so far. The problem
comes within the individual case statements... if A[7:0] is a certain
value (h00 and h20 come to mind), I want to output that same value
onto B[7:0].

If I simply put as my statement B[7:0] <= A[7:0] or if I do B[7:0] =
A[7:0] it freaks out, with 2 errors per instance of such statements.
Am I declaring these wrong? Is there something more involved? If more
is needed, I'll post the errors themselves tomorrow morning, but I
figure I'm doing something boneheaded enough that even with this much,
it should be obvious.

Any and all help appreciated.

Have you declared a reg for your output? I don't know if you *can*
declare "inout reg [7:0] B" in your port-list. I would use another
register internally and assign that to the inout bus.

Declaration:
reg [7:0] rB;

In the case statement:
rB <= A;

Outside the always block:
assign B = tristate? 8'hzx : rB;

 

[Jonathan Bromley]

On Thu, 23 Aug 2007 13:08:51 GMT,
John_H <newsgroup@johnhandwork.com> wrote:

Have you declared a reg for your output? I don't know if you *can*
declare "inout reg [7:0] B" in your port-list.

No, you can't. inout ports *must* be nets, both inside
and outside the module boundary; consequently, they *must*
be driven by continuous assign statements or by some other form
of structural driver (e.g. by connection to another module's
output or inout port). It is *never* possible to make
procedural assignment to an inout port.

I would use another
register internally and assign that to the inout bus.

Declaration:
reg [7:0] rB;

In the case statement:
rB <= A;

Outside the always block:
assign B = tristate? 8'hzx : rB;

Something of that kind, yes. And then it's merely
necessary to generate the correct logic for your
tristate enable signal.
--
Jonathan Bromley, Consultant

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The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[glen herrmannsfeldt]

John Oyler wrote:

I'm using xilinx's webpack software to try to synthesize. Most of my
stuff is syntactically correct, removing a few problem lines will let
it synth with no errors or warnings. However, one of the important
things I've still not figured out what to do.

The XC4000 series devices had real tristate buffers inside,
which could be used like TTL tristate buffers. Also, the IO
blocks can be configured as tristate drivers.

inout nets can be used to implement tristate buses in verilog,
and the synthesis tools should be able to figure that out.
If you write something that can't be implemented as tristate
logic, then I wouldn't be surprised to see complaints.

I've declared two busses as inout, each 8 bits wide. I have my main
loop set for clk's posedge, and within that I have a case select
checking the value of data bus A. All is good so far. The problem
comes within the individual case statements... if A[7:0] is a certain
value (h00 and h20 come to mind), I want to output that same value
onto B[7:0].

It might be that you have to assign Z to B in the other cases.
I have done it with structural logic. Others have suggested that it
might not work in other forms. If it can't figure out that A is
currently driven or not, then it might not be able to assign B.

-- glen