Beginner: Simple D latch

[M.A.Khader]

HI,

I was solving the following question and came up with a solution. I
am a beginner and sloving the exercises from Ashenden's "Designer's
guide for VHDL".
DEVELOP A BEHAVIORAL MODEL FOR A D LATCH WITH A CLOCK-TO-OUTPUT
PROPAGATION DELAY OF 3NS AND DATA-TO-OUTPUT PROPAGATION DELAY OF 4NS.

What I worte is ......
Entity D_latch IS
Port(d,clk : in std_ulogic;
q : out std_ulogic);
End entity D_latch;
Architecture behave of D_latch is
Begin
latch: Process is
Begin
if(clk='1') then
q<=d after 4ns;
end if;
wait on clk,d;
end process latch;
End architecture behave;
I am not able to incorporate clock-to-output delay of 3 ns. Where
should I insert this delay to emulate this .

Thanks in advance.

Regards,
akfami.

 

[Niels Bakker]

M.A.Khader wrote:

HI,

I was solving the following question and came up with a solution. I
am a beginner and sloving the exercises from Ashenden's "Designer's
guide for VHDL".
DEVELOP A BEHAVIORAL MODEL FOR A D LATCH WITH A CLOCK-TO-OUTPUT
PROPAGATION DELAY OF 3NS AND DATA-TO-OUTPUT PROPAGATION DELAY OF 4NS.

What I worte is ......
Entity D_latch IS
Port(d,clk : in std_ulogic;
q : out std_ulogic);
End entity D_latch;
Architecture behave of D_latch is
Begin
latch: Process is
Begin
if(clk='1') then
q<=d after 4ns;
end if;
wait on clk,d;
end process latch;
End architecture behave;
I am not able to incorporate clock-to-output delay of 3 ns. Where
should I insert this delay to emulate this .

Thanks in advance.

Regards,
akfami.

Might this be something?

--Niels Bakker

library ieee;
use ieee.std_logic_1164.all;

Entity D_latch IS
Port(d,clk : in std_ulogic;
q : out std_ulogic);
End entity D_latch;

Architecture behave of D_latch is
Begin
latch: Process is
Begin
if clk='1' then
if d'event then -- latch transparent and change of data
q<=d after 4 ns;
elsif clk'event then -- latch is being enabled
q<=d after 3 ns;
end if;
end if;
wait on clk,d;
end process latch;

end architecture behave;

 

[Ralf Hildebrandt]

M.A.Khader wrote:

latch: Process is
Begin
if(clk='1') then
q<=d after 4ns;
end if;
wait on clk,d;
end process latch;

I am not able to incorporate clock-to-output delay of 3 ns. Where
should I insert this delay to emulate this .

Take the template for synthesizable latches:

process(clk,d)
begin
if(clk='1') then
q<=d;
end if;
end process;

Remember: There is no reset included.
If you want to apply a delay for simulation:

process(clk,d)
begin
if(clk='1') then
q<=d after 3 ns; -- not synthesizable
end if;
end process;


Ralf

 

[ivailokroumov]

Hi M.A.Khader
When You Stady delays, you need to understanding at first time that they
are very difficult to be SYNTHESIZEable when you are going to write
complex models. At first time you need to know that on your level you have
three basic types delays.
1. The Internal Delay model
All components in digital circuits have a certain amount of inertia. For
Example, it takes a finit amount of time and a certain amount of energy
for the output of a gate to respond to a change on the input. The VHDL
language uses the propagation delay through the component as the default
pulse rejaction width.
sum <= reject 2 ns inertial (a xor b) after 5 ns;

2. The transport delay model
When we connect devices we use wire to make connection and to send
information. But wire are material elements, and they have resistance.
This can be shown as that:
sum <= transport (a xor b) after 5 ns;

3 Delta delay
Dhis type of delays are unspecifyed. You need just to write:
sum <= (a xor b);

Don't forget to leave space between value and dementions, because they are
Physical type;

You can solve your task in this manner:

entity D_latch IS
port(d,clk : in std_ulogic;
q : out std_ulogic);
end entity D_latch;

architecture behav of D_latch is
Begin
latch: Process is
Begin
if clk='1' then
if d'event then
q<=d after 4 ns;
elsif clk'event then
q<=d after 3 ns;
end if;
end if;
wait on clk,d;
end process latch;

VHDL language is key unsensitive.

Best Regards
Ivaylo Krumov