beginner in VHDL

[Hans K Eide]

Help needed…

Hi, my name is Hans Kristian, and I am a student at the University of
Bergen, in Norway. As a part of my master in physics, I am going to
examine a communication standard called ‘space wire’. It is written in
VHDL.

My problem is that I have no previous experience with that language, nor
have I been working with FPGAs. My background is automation engineer,
and the only language I know well is C++. My mentor is a theorist, and
can not help me with the practical things.

If some one could give me an advice where to start, I would be grateful.
I am sitting here with an ALTERA Stratix development board, and a thick
book ‘The Designer’s Guide To VHDL’ written by Peter Ashenden, but
really don’t know where to start.

 

[Eric Smith]

Hans K Eide <hans.eide@student.uib.no> writes:

If some one could give me an advice where to start, I would be
grateful. I am sitting here with an ALTERA Stratix development board,
and a thick book "The Designer's Guide To VHDL" written by
Peter Ashenden, but really don't know where to start.

You've got the right book, you just need to read, study, and try the
exercises. There's not any better way to learn it, AFAIK.

 

[Brian Drummond]

On Sat, 20 Nov 2004 18:26:00 +0100, Hans K Eide
<hans.eide@student.uib.no> wrote:

Help needed…

Hi, my name is Hans Kristian, and I am a student at the University of
Bergen, in Norway. As a part of my master in physics, I am going to
examine a communication standard called ‘space wire’. It is written in
VHDL.

If some one could give me an advice where to start, I would be grateful.
I am sitting here with an ALTERA Stratix development board, and a thick
book ‘The Designer’s Guide To VHDL’ written by Peter Ashenden, but
really don’t know where to start.

Right author; right book for a reference; but something of an elephant.
Google for Ashenden and "VHDL Cookbook" which you can read through much
more quickly and get started.

- Brian

 

[Neo]

Hi hans,
The book is a really good one but hard on beginners. You can check out
the VHDL book from douglass perry which will take you through the
process much faster of course assuming you are conversant with digital
concepts.
go to the link below and download the free vhdl/verilog turorial which
is quite good.
http://www.aldec.com/Downloads/
If you have got specific questions you can email me.


Neo.

 

[Neo]

Hi hans,
The book is a really good one but hard on beginners. You can check out
the VHDL book from douglass perry which will take you through the
process much faster of course assuming you are conversant with digital
concepts.
go to the link below and download the free vhdl/verilog turorial which
is quite good.
http://www.aldec.com/Downloads/
If you have got specific questions you can email me.


Neo.

 

[Neo]

Hi hans,
The book is a really good one but hard on beginners. You can check out
the VHDL book from douglass perry which will take you through the
process much faster of course assuming you are conversant with digital
concepts.
go to the link below and download the free vhdl/verilog turorial which
is quite good.
http://www.aldec.com/Downloads/
If you have got specific questions you can email me.


Neo.

 

[Ian Lang]

Hans K Eide wrote:

Help needed…

Hi, my name is Hans Kristian, and I am a student at the University of
Bergen, in Norway. As a part of my master in physics, I am going to
examine a communication standard called ‘space wire’. It is written in
VHDL.

My problem is that I have no previous experience with that language, nor
have I been working with FPGAs. My background is automation engineer,
and the only language I know well is C++. My mentor is a theorist, and
can not help me with the practical things.

If some one could give me an advice where to start, I would be grateful.
I am sitting here with an ALTERA Stratix development board, and a thick
book ‘The Designer’s Guide To VHDL’ written by Peter Ashenden, but
really don’t know where to start.

Take a look at these articles for a few tips:
http://www.designabstraction.co.uk/HTML/articles.htm
Regards,
Ian Lang.

 

[Mike Treseler]

Ian Lang wrote:

Take a look at these articles for a few tips:
http://www.designabstraction.co.uk/HTML/articles.htm

Your article "Advanced Synthesis Techniques" is excellent.
I would recommend it to anyone interested in writing good vhdl or
verilog code for synthesis.

One suggestion: Consider updating the examples
to use the ieee.numeric_std library.

Thanks for the posting.

-- Mike Treseler

 

[Ian Lang]

"Mike Treseler" <mike_treseler@comcast.net> wrote in message
news:HsudnepCqZX6czTcRVn-sA@comcast.com...

Ian Lang wrote:

Take a look at these articles for a few tips:
http://www.designabstraction.co.uk/HTML/articles.htm

Your article "Advanced Synthesis Techniques" is excellent.
I would recommend it to anyone interested in writing good vhdl or verilog
code for synthesis.

One suggestion: Consider updating the examples
to use the ieee.numeric_std library.

Thanks for the posting.

-- Mike Treseler

Thanks for the feedback Mike. Glad you like it.
At the risk of showing my ignorance, why do you prefer numeric_std to
std_logic_arith? I have to say, I'm a bit inconsistent in my choice of
which to use.
Regards,
Ian Lang

 

[Mike Treseler]

Ian Lang wrote:

Thanks for the feedback Mike. Glad you like it.
At the risk of showing my ignorance, why do you prefer numeric_std to
std_logic_arith?

Mainly because std_logic_arith is vendor controlled
while numeric_std is a true ieee standard.

Here's a recent thread on the subject
http://groups.google.com/groups?q=vhdl+arith+Hubberstey+paris


-- Mike Treseler

 

[MikeTreseler]

Actually the update is quite simple:
I commented out the std_logic_arith and std_logic_unsigned
USE statements, and rtl.vhd still compiles fine.
So, no numeric functions are used in the example.

Also, try assigning the port outputs directly from the
variable values as shown below, and add these
variables to the reset clause so the values are
correct for both the reset and clock cases.

-- Mike Treseler

______________________

-- s_serialOut <= v_serialOut;
-- s_readData <= v_readData;
end if;
serialOut <= v_serialOut; -- new
readData <= v_readData; -- new
end process clockedLogic;

-- serialOut <= s_serialOut;
-- readData <= s_readData;
end RTL;
______________________

 

[Ken Smith]

In article <cnnun7$14l3$1@toralf.uib.no>,
Hans K Eide <hans.eide@student.uib.no> wrote:

Help needed…

Hi, my name is Hans Kristian, and I am a student at the University of
Bergen, in Norway. As a part of my master in physics, I am going to
examine a communication standard called ‘space wire’. It is written in
VHDL.

My problem is that I have no previous experience with that language, nor
have I been working with FPGAs. My background is automation engineer,
and the only language I know well is C++. My mentor is a theorist, and
can not help me with the practical things.

If some one could give me an advice where to start, I would be grateful.
I am sitting here with an ALTERA Stratix development board, and a thick
book ‘The Designer’s Guide To VHDL’ written by Peter Ashenden, but
really don’t know where to start.

Read the book and start with something about this complex:

library ieee;
use ieee.std_logic_1164.all;

entity InverterConnect is port(
A : in std_logic;
B : out std_logic);
end InverterConnect;

architecture InverterLogic of InverterConnect is
begin
B <= not A;
end;



Chances are you will only need about 25% of all of VHDL to get useful work
done. Do a few examples and then pick a small bit of your actual project
to do. After you've made something work, build your knowledge up from
there. "When eating an elephant take it one bite at a time"

I'm just about done with my first ever VHDL project. Its on the order of
5000 lines. I don't recomend something that big the first time out the
gate. There's just too much to keep in your head.


--
--
kensmith@rahul.net forging knowledge

 

[john]

Hi,
I would suggest that

Reading the book first and know VHDL is not a good idea at all! HDL is
a hardware discription language. Try to buit a small electronics
circuit like casacade three 8- bit counters and connect them together
through wires. buy 8 bit counters, hook them to power supply u know
...u can find lots of electronics circuit examples on the internet and
then simulate the same circuit in VHDL and compare the result and
during this project read the things form the book which will help you
in this small project.. Remember its not a programming language like
C++ its a discription langauge. so learn how to design electronics
hardware and then on that knowledge learn how to discribe that
hardware in VHDL...

Regards
john


Hans K Eide <hans.eide@student.uib.no> wrote in message news:<cnnun7$14l3$1@toralf.uib.no>...

Help needed…

Hi, my name is Hans Kristian, and I am a student at the University of
Bergen, in Norway. As a part of my master in physics, I am going to
examine a communication standard called ‘space wire’. It is written in
VHDL.

My problem is that I have no previous experience with that language, nor
have I been working with FPGAs. My background is automation engineer,
and the only language I know well is C++. My mentor is a theorist, and
can not help me with the practical things.

If some one could give me an advice where to start, I would be grateful.
I am sitting here with an ALTERA Stratix development board, and a thick
book ‘The Designer’s Guide To VHDL’ written by Peter Ashenden, but
really don’t know where to start.

 

[Najeem Lawal]

Hans,

This statement is very true.

Chances are you will only need about 25% of all of VHDL to get useful work
done. Do a few examples and then pick a small bit of your actual project
to do. After you've made something work, build your knowledge up from
there. "When eating an elephant take it one bite at a time"

Like your knowledge of C++ you probably should not all the classes and
libraries to implement an application. But you have to be very close
to a good reference book like the one u have. I have a copy too.

Of course you must go beyond 25% when you need take on the 'elephant'
projects.

Regards,

Najeem

kensmith@green.rahul.net (Ken Smith) wrote in message news:<cnot4r$u0d$4@blue.rahul.net>...

In article <cnnun7$14l3$1@toralf.uib.no>,
Hans K Eide <hans.eide@student.uib.no> wrote:
Help needed?

Hi, my name is Hans Kristian, and I am a student at the University of
Bergen, in Norway. As a part of my master in physics, I am going to
examine a communication standard called ?space wire?. It is written in
VHDL.

My problem is that I have no previous experience with that language, nor
have I been working with FPGAs. My background is automation engineer,
and the only language I know well is C++. My mentor is a theorist, and
can not help me with the practical things.

If some one could give me an advice where to start, I would be grateful.
I am sitting here with an ALTERA Stratix development board, and a thick
book ?The Designer?s Guide To VHDL? written by Peter Ashenden, but
really don?t know where to start.


Read the book and start with something about this complex:

library ieee;
use ieee.std_logic_1164.all;

entity InverterConnect is port(
A : in std_logic;
B : out std_logic);
end InverterConnect;

architecture InverterLogic of InverterConnect is
begin
B <= not A;
end;



Chances are you will only need about 25% of all of VHDL to get useful work
done. Do a few examples and then pick a small bit of your actual project
to do. After you've made something work, build your knowledge up from
there. "When eating an elephant take it one bite at a time"

I'm just about done with my first ever VHDL project. Its on the order of
5000 lines. I don't recomend something that big the first time out the
gate. There's just too much to keep in your head.


--

 

[rickman]

Let me toss in my two cents worth. From your description, it is not
clear if the code you want to examine is behavioral VHDL which is
written like a C program to describe the behavior of a system (and is
not necessarily synthesizable) or if your code is RTL form which can be
synthesized. You also do not say if you will be writing new code or if
you just need to learn what the existing code does.

If you have behavioral code that is not synthesized (put in a form to
load into your hardware) and you do not need to write any code, you
don't have a hard job ahead. The fact that you know a programming
language is a head start. But you need to learn how VHDL describes
"concurrent" statement which are treated as if they all run in parallel
rather than sequentially like C. And keep in mind that "processes" are
nothing like subroutines. They are used to describe sections of
hardware that are more easily described with sequential statements
rather than parallel ones. To modularize your code use entities.

If I assume that you need to write your own RTL (register transfer
language) code to build hardware, then you have a much tougher job
ahead. In that case I advise that you focus on learning how to design
hardware and then learn how to *describe* the hardware in VHDL. One of
the problems I often see is when a designer trys to think in the VHDL
language without consideration of what hardware the tool should be
making from the code. Instead, I always design my hardware first,
sometimes down to the detailed equations to go into a given LUT, and
then write my VHDL to describe exactly this arrangement of hardware.

Finally, don't bother with a board or FPGA until you actually need to
make something happen in the real world. You can work much, much better
in a simulator until you have the design working the way it should.
Only then should you bother to synthesize it and test it in hardware.
Hardware is much harder to debug.

Good luck and let us know how it goes...


john wrote:

Hi,
I would suggest that

Reading the book first and know VHDL is not a good idea at all! HDL is
a hardware discription language. Try to buit a small electronics
circuit like casacade three 8- bit counters and connect them together
through wires. buy 8 bit counters, hook them to power supply u know
..u can find lots of electronics circuit examples on the internet and
then simulate the same circuit in VHDL and compare the result and
during this project read the things form the book which will help you
in this small project.. Remember its not a programming language like
C++ its a discription langauge. so learn how to design electronics
hardware and then on that knowledge learn how to discribe that
hardware in VHDL...

Regards
john

Hans K Eide <hans.eide@student.uib.no> wrote in message news:<cnnun7$14l3$1@toralf.uib.no>...
Help needed…

Hi, my name is Hans Kristian, and I am a student at the University of
Bergen, in Norway. As a part of my master in physics, I am going to
examine a communication standard called ‘space wire’. It is written in
VHDL.

My problem is that I have no previous experience with that language, nor
have I been working with FPGAs. My background is automation engineer,
and the only language I know well is C++. My mentor is a theorist, and
can not help me with the practical things.

If some one could give me an advice where to start, I would be grateful.
I am sitting here with an ALTERA Stratix development board, and a thick
book ‘The Designer’s Guide To VHDL’ written by Peter Ashenden, but
really don’t know where to start.

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX