E
Evan Lavelle
Guest
Does anyone actually implement `begin_keywords/`end_keywords? To
handle these, your lexer has to dynamically change its keyword list on
the fly, which precludes anything which is lex-like. The spec also
says "The directives do not affect the semantics, tokens, and other
aspects of the Verilog language." So, presumably, the user could
request 1995 keywords, use 'generate' as an identifer, and then expect
a generate statement to work?
These can also only be specified "outside of a design element (module,
primitive, or configuration)". A lexer doesn't have any semantic
information - how is it going to know?
Evan
handle these, your lexer has to dynamically change its keyword list on
the fly, which precludes anything which is lex-like. The spec also
says "The directives do not affect the semantics, tokens, and other
aspects of the Verilog language." So, presumably, the user could
request 1995 keywords, use 'generate' as an identifer, and then expect
a generate statement to work?
These can also only be specified "outside of a design element (module,
primitive, or configuration)". A lexer doesn't have any semantic
information - how is it going to know?
Evan