baud_generator (16x baud) used in UART transmitter logic

[_Xilinx]

For http://www.ti.com/lit/ds/symlink/pc16550d.pdf#page=17 , how is the output of baud_generator (16x baud) used in transmitter logic ?

I only see there is a transmitter timing control block in the functional block diagram, but I am not sure how it works exactly. Anyone ?

 

[Michael Kellett]

_Xilinx:

For http://www.ti.com/lit/ds/symlink/pc16550d.pdf#page=17 , how is the
output of baud_generator (16x baud) used in transmitter logic ?

I only see there is a transmitter timing control block in the
functional block diagram, but I am not sure how it works exactly. Anyone

?

I think you'll need to Google about a bit on this one - the chip is old
enough for its insides to be public.

Some how I don't think you are actually related to the Xilinx without a
leading underscore so perhaps you should think of a more original handle


MK

 

[rickman]

_Xilinx wrote on 6/1/2017 8:30 AM:

For http://www.ti.com/lit/ds/symlink/pc16550d.pdf#page=17 , how is the output of baud_generator (16x baud) used in transmitter logic ?

I only see there is a transmitter timing control block in the functional block diagram, but I am not sure how it works exactly. Anyone ?

The baud rate generator defines how fast the UART circuit works. There are
two ways of providing this control. One is to generate a clock for the UART
which goes to the clock input on each FF. This is typically a square wave
(or close to one). The other is to generate an enable signal that lets the
FFs in the UART to run from a master clock with actions disabled in the FFs
on all cycles except for the ones enabled by the baud clock. This means the
enable must be active for only one clock of many.

--

Rick C

 

[Gabor]

On Thursday, 6/1/2017 8:30 AM, _Xilinx wrote:

For http://www.ti.com/lit/ds/symlink/pc16550d.pdf#page=17 , how is the output of baud_generator (16x baud) used in transmitter logic ?

I only see there is a transmitter timing control block in the functional block diagram, but I am not sure how it works exactly. Anyone ?

It seems pretty obvious from the text. You give the chip a clock up to
24 MHz. Then there's a register that can divide that clock by any
whole number up to 65535. The transmitter and receiver bit rate will
be 1/16th of the divided clock frequency. For a simple UART, you only
need to be within about +/- 1% of nominal baud rate to work. So if your
input clock is not a nice multiple of the desired baud rate it's best
if the clock is at least 800 times the desired rate. If your intent
is to use this as a standard PC peripheral, your input clock should
match the input clock frequency used on PC motherboards.

Both transmit and receive sections of the UART run from the 16x clock
created by the baud rate generator. For transmitting it may simply
use a free-running divide by 16 to generate the bit-rate clock. For
the receiver, the sampling rate is 16x the baud rate. Then the falling
edge of the start bit is used to reset a counter that creates the sample
time for subsequent bits (this is a simplified description).

If your intent is to re-create the guts of this chip in an FPGA, then
you can take rickman's suggestion of using a clock enable from the baud
rate generator rather than creating a clock.

--
Gabor