S
sundar
Guest
hi all,
1) how does it matter for a cpld when i declare a constant or signal
2) what is the difference if i mention default value while
declaration /without declaration
3)
difference between below piece of tristate code
output <= a when enable= '1' else ''z';
and using primitive
tri port map
(
a_in <= a,
oe <= enable,
a_out <= output
)
which is better why?
4) output <= a when (expression1)
else b when (expr2)
else....
...
else n when (exprn)
what is the diff if this combo logic is inside a process block
5) whats the diff between
if ( a and b and c and d)
case x
1:
2:
3:
4:
default
and
if (a and b and c and d and x1)
elseif (a and b and c and d and x2)
elseif (a and b and c and d and x3)
elseif (a and b and c and d and x4)
else
note that internal case x is used as x1,x2,x3 and x4 respectively
pls share your thots
rgs,
sundar
1) how does it matter for a cpld when i declare a constant or signal
2) what is the difference if i mention default value while
declaration /without declaration
3)
difference between below piece of tristate code
output <= a when enable= '1' else ''z';
and using primitive
tri port map
(
a_in <= a,
oe <= enable,
a_out <= output
)
which is better why?
4) output <= a when (expression1)
else b when (expr2)
else....
...
else n when (exprn)
what is the diff if this combo logic is inside a process block
5) whats the diff between
if ( a and b and c and d)
case x
1:
2:
3:
4:
default
and
if (a and b and c and d and x1)
elseif (a and b and c and d and x2)
elseif (a and b and c and d and x3)
elseif (a and b and c and d and x4)
else
note that internal case x is used as x1,x2,x3 and x4 respectively
pls share your thots
rgs,
sundar