Basic question

M

m

Guest
Forgive me for asking something very basic. I bought two books on
VHDL and they just jump in and use this terminology without explaning
what it does. Also, I come from ten years of Verilog (I come in
peace).

signal A : unsigned( 7 downto 0);
..
..
..
A <= (others => '0');


My guess is that (others => '0') simply assigns hex 00 to A.


Why can't or wouldn't one just say "A <= '0';" or something similarly
simple?
Why is "others" required?


Thank you,


-Martin
 
On Sep 27, 8:06 am, m <martin.use...@gmail.com> wrote:
Forgive me for asking something very basic. I bought two books on
VHDL and they just jump in and use this terminology without explaning
what it does. Also, I come from ten years of Verilog (I come in
peace).

signal A : unsigned( 7 downto 0);
.
.
.
A <= (others => '0');

My guess is that (others => '0') simply assigns hex 00 to A.

Why can't or wouldn't one just say "A <= '0';" or something similarly
simple?
Why is "others" required?

Thank you,

-Martin
Click to expand...
When "A" is declared to std_logic, " A <= '0'; " is correct. You have
declared A to an array,
"others" is for filling complex objects, like arrays. Yo may write " A
<= "00000000"; " also.
"others" is useful when the number of elements in array are changing

For example when you'd like to change to declaration to unsigned(8
downto 0) and you are using others, don't need to change " A <=
(others=>'0')" line, anyway need to write " A <= "000000000"; ", so
you dont need to change the code when you are using others.

J
 
On Fri, 26 Sep 2008 23:06:11 -0700 (PDT), m <martin.usenet@gmail.com>
wrote:

Forgive me for asking something very basic. I bought two books on
VHDL and they just jump in and use this terminology without explaning
what it does. Also, I come from ten years of Verilog (I come in
peace).

signal A : unsigned( 7 downto 0);
.
.
.
A <= (others => '0');


My guess is that (others => '0') simply assigns hex 00 to A.


Why can't or wouldn't one just say "A <= '0';" or something similarly
simple?
Why is "others" required?
Click to expand...
You cannot assign A <= '0' because '0' is a 1-bit value, and A is an
array of 8 bits (8 std_logic values to be more pedantic), so you need an
8-bit array to assign to A.

(This means that assigning a 7-bit array to A will be flagged as an
error, the intent is to catch errors as early as possible)

A <= X"00"; -- will work, until you change the size of A.
A <= "0000_0000"; -- will work, ditto,
-- the '_' is optional but keeps you from getting lost

Or you can assign an array aggregate, as
A <= ('0', '0', '0', '0', '0', '0', '0', '0');
where the entire array is described using positional association,
namely the first value goes into the first bit. Again the array size has
to match A.

Or you can use named association. For example if bit 3 of the array is
'1' and bit 5 is 'X',
A <= (3 => '1', 5 => 'X', others => '0');
and in named association, 'others' is a catch-all clause for any bits
you didn't name explicitly. Named association is immensely powerful,
though overkill for this little example.
For example, the above could be described as
A <= "00X01000";
but what about this example...

package bit_faults is
-- this package is written by a random test generator
constant SA1 : integer := 3;
constant X_bit:integer := 5;
end package;

use work.bit_faults.all;
A <= (SA1 => '1', X_bit => 'X', others => '0');

Now
A <= (others => '0');
is thus just a special case of named association. Which has the useful
property that it still works when you change the size of A.

Named association can also be used for argument lists to functions and
procedures, as well as generic maps and port maps in components. (Can
you use "others" in all these cases?)

- Brian
 
m <martin.usenet@gmail.com> writes:

Forgive me for asking something very basic. I bought two books on
VHDL and they just jump in and use this terminology without explaning
what it does. Also, I come from ten years of Verilog (I come in
peace).

signal A : unsigned( 7 downto 0);
.
.
.
A <= (others => '0');


My guess is that (others => '0') simply assigns hex 00 to A.


Why can't or wouldn't one just say "A <= '0';" or something similarly
simple?
Why is "others" required?
Click to expand...
Several others have pointed out fairly clearly that '0' is a single
bit value, and cannot be assigned to an array with 8 elements.

But, they've neglected to point out that 'others' is a shorthand for
denoting all the 'other' values for the LHS of an expression.

This is especially useful when you've got some type of 'generic'
programming which can be resized during different compilations.

Let's say you've got a CPU that can be 16 or 32 bits. And, let's say
that the the result of reading non-existent memory is a value with all
bits set to one.

So, your result can be 32 or 16 bits:

result : std_logic_vector(15 downto 0);
result <= X"FFFF"; -- 16-bit result

or result : std_logic_vector(31 downto 0);
result <= X"FFFFFFFF"; -- 32-bit result

There is no C-like conditional compilation, so you've got to be able
to do something generic which will compile correctly for both sizes.

result <= (others => '1'); -- works for any size of 'result'.

thutt
http://www.harp-project.com/
--
Hoegaarden!
 
On Sat, 27 Sep 2008 10:45:24 -0700 (PDT), m <martin.usenet@gmail.com>
wrote:

Thank you. Very helpful explanations. Just trying to get my head
around VHDL as I have to work some some code and translate it into
Verilog for my project.

Any suggestions on a book/books that might fill-in the gaps. I
purchased the following titles:
Click to expand...
Ashenden, "Designer's Guide to VHDL" should definitely be on the list.

- Brian
 
Thank you. Very helpful explanations. Just trying to get my head
around VHDL as I have to work some some code and translate it into
Verilog for my project.

Any suggestions on a book/books that might fill-in the gaps. I
purchased the following titles:

"FPGA prototyping by VHDL examples. Xilinx Spartan-3 Version" by Pong
P. Chu
"Circuit design with VHDL" by Volnei A. Pedroni

I was surprised that neither book covered this basic (others => x)
construct. They go ahead and start using it by the second or third
example with no explanation whatsoever. If you come from --forgive
me-- "conventional" languages, VHDL can look very cryptic. I would
think that an introductory book would be careful about not using new
constructs until they are addressed in the text. Perhaps I bought the
wrong books?
Thanks,

-Martin
 
On 27 Sep 2008 09:16:06 -0700, thutt <thutt151@comcast.net> wrote:


There is no C-like conditional compilation, so you've got to be able
to do something generic which will compile correctly for both sizes.

result <= (others => '1'); -- works for any size of 'result'.
Click to expand...
I'm tempted to turn that statement around:

you can do something generic which will compile correctly for both
sizes, so there's no need for C-like conditional compilation.

Perish the thought that anyone would mistake that conditional
compilation quagmire for a good thing.

- Brian
 
On Sun, 28 Sep 2008 13:11:05 -0700 (PDT), spam@oxfordbromley.plus.com
wrote:

On Sep 27, 1:34 pm, Brian Drummond <brian_drumm...@btconnect.com
wrote:

A <= "0000_0000"; -- will work, ditto,
-- the '_' is optional but keeps you from getting lost

Sorry to nit-pick, but I don't think that's true.
.... By contrast, B"0000_0000" will work
in the way you suggest, because of the way the
lexical substitution is defined to operate.
Click to expand...
Thanks for the correction.

- Brian
 
On Sep 27, 1:34 pm, Brian Drummond <brian_drumm...@btconnect.com>
wrote:

A <= X"00"; -- will work, until you change the size of A.
Click to expand...
Right. But please note that X"00" actually gets translated
(lexically substituted) into "00000000", four 0s for each
0 in the hex value. So when using X"...." you MUST be
creating a value with 4N elements. Tedious but true.

A <= "0000_0000"; -- will work, ditto,
-- the '_' is optional but keeps you from getting lost
Click to expand...
Sorry to nit-pick, but I don't think that's true.
In plain double-quotes like that, you have a 9-element
string which can only translate into a 9-element vector
of some enumeration type that has '0' and '_' in its
set of available literals. The latter is illegal for
std_logic. By contrast, B"0000_0000" will work
in the way you suggest, because of the way the
lexical substitution is defined to operate.

It's all a bit tiresome, but very consistent :)

I'm not using my normal news service so may have missed
some posts, but I hope someone has also pointed out to
the OP that it may be better to write

result <= std_logic_vector(to_unsigned(0, result'length));

(depending on what he's trying to do) although that
requires you to add

use ieee.numeric_std.all;

to the context clauses.
--
Jonathan Bromley
 
m wrote:
Thank you. Very helpful explanations. Just trying to get my head
around VHDL as I have to work some some code and translate it into
Verilog for my project.

Any suggestions on a book/books that might fill-in the gaps. I
purchased the following titles:

"FPGA prototyping by VHDL examples. Xilinx Spartan-3 Version" by Pong
P. Chu
"Circuit design with VHDL" by Volnei A. Pedroni

I was surprised that neither book covered this basic (others => x)
construct. They go ahead and start using it by the second or third
example with no explanation whatsoever. If you come from --forgive
me-- "conventional" languages,
Click to expand...
Unless that conventional language was Ada :)

VHDL can look very cryptic. I would
think that an introductory book would be careful about not using new
constructs until they are addressed in the text. Perhaps I bought the
wrong books?
Thanks,

-Martin
Click to expand...
I tend to recommend "Digital System Design with VHDL" by Mark Zwolinski.

Also if you can get hold of it "HDL Chip Design" by Doug Smith shows
examples of Verilog and VHDL code side-by-side. However it's out of
print so you'd have to buy it second hand,

Alan

--
Alan Fitch
Doulos
http://www.doulos.com
 
m wrote:
Forgive me for asking something very basic. I bought two books on
....

Why can't or wouldn't one just say "A <= '0';" or something similarly
simple?


Short answer: VHDL is overly strict, and 'simple' can rarely be used to
Click to expand...
describe its syntax. Coming from the Verilog world, you might find this
annoying. -Kevin
 
On Sep 28, 3:11 pm, s...@oxfordbromley.plus.com wrote:
I'm not using my normal news service so may have missed
some posts, but I hope someone has also pointed out to
the OP that it may be better to write

  result <= std_logic_vector(to_unsigned(0, result'length));
Click to expand...
Since the OP was assigning a vector of type unsigned (assuming
numeric_std.unsigned), it would be better for him to write:

a <= to_unsigned(0, a'length);

Or if you are typographically challenged and hoping the synthesis tool
will be kind to you:

a<=a-a;

uses only 5 keys and 7 characters ;^)

Andy
 
Brian Drummond <brian_drummond@btconnect.com> writes:

On 27 Sep 2008 09:16:06 -0700, thutt <thutt151@comcast.net> wrote:



There is no C-like conditional compilation, so you've got to be able
to do something generic which will compile correctly for both sizes.

result <= (others => '1'); -- works for any size of 'result'.

I'm tempted to turn that statement around:

you can do something generic which will compile correctly for both
sizes, so there's no need for C-like conditional compilation.

Perish the thought that anyone would mistake that conditional
compilation quagmire for a good thing.
Click to expand...
I don't consider it a good thing, but neither do I think that VHDL's
'generate' statement wins any awards either.

thutt


--
Hoegaarden!
 
On Sep 27, 7:45 pm, m <martin.use...@gmail.com> wrote:
"FPGA prototyping by VHDL examples. Xilinx Spartan-3 Version" by Pong
P. Chu
"Circuit design with VHDL" by Volnei A. Pedroni

I was surprised that neither book covered this basic (others => x)
construct. They go ahead and start using it by the second or third
example with no explanation whatsoever. If you come from --forgive
Click to expand...
I got the Pedroni book, too, and found it irritating that he didn't
take time to explain it. As we see from this thread, it doesn't take
many words to explain what the others clause is and how it works.
Pedroni does give more examples of the use of others in his book than
other authors, and they are listed in the index, which is not so
common in other books.

I am struggling to try to solve a problem that I think is related so
I'll throw it in here: I want to write a module using generics to
configure different sizes of a std_logic array where each signal in
the array is anded with one single mask bit.

signal chip_en : std_logic_vector(g_ndevices-1 downto 0); -- active
low
signal unmask_chip_en : std_logic;

debug(12 downto 9) <= "1111" and chip_en and unmask_chip_en;

Rtlvision from Concept Engineering accepts the assignment and shows
logic doing what I want to do: and'ing each bit of chip_en with
unmask_chip_en for all cases of g_ndevice. If g_ndevice is smaller
than 4, the unassigned bits in debug(12 downto 9) is set to 1.
This doesn't help me as Xilinx XST complains that the sizes of the
signals have to be the same. Is there a simple way to solve this, or
will I have to use if/then/elsif for each of the possibilities in
g_ndevice?

--
Svenn
 
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