P
parag
Guest
If I am using debug during the simultion of the following RTL, and
there forcing a vallue using PLI on the signal inpad inside the
tran_mod, Should this be propagated to the wire pad.
I am a software engineer and have basic understanding of bheavioral
and other gate level modeling, But switch level modelling is still
elusive to me. Can some one please help
module top;
wire inpad ;
wire pad;
reg i ,j;
assign inpad = i;
assign pad = j;
tran_mod t1 (inpad,pad);
initial
begin
#1 i = 1;
#1 j = 0;
#10
i= 0;
j = 1;
end
endmodule
module tran_mod (inout inpad, inout pad);
tran t1(inpad,pad);
initial
$monitor( inpad, pad);
bot b1(inpad);
endmodule
module bot(inout b1);
always @(b1)
$display("the valuepropagation comes here\n");
endmodule
there forcing a vallue using PLI on the signal inpad inside the
tran_mod, Should this be propagated to the wire pad.
I am a software engineer and have basic understanding of bheavioral
and other gate level modeling, But switch level modelling is still
elusive to me. Can some one please help
module top;
wire inpad ;
wire pad;
reg i ,j;
assign inpad = i;
assign pad = j;
tran_mod t1 (inpad,pad);
initial
begin
#1 i = 1;
#1 j = 0;
#10
i= 0;
j = 1;
end
endmodule
module tran_mod (inout inpad, inout pad);
tran t1(inpad,pad);
initial
$monitor( inpad, pad);
bot b1(inpad);
endmodule
module bot(inout b1);
always @(b1)
$display("the valuepropagation comes here\n");
endmodule