S
Sunita Jain
Guest
Hello,
I have a small Q regarding Verilog.
Since we can't use structural and behavioral styles of modelling
together, is there any method to instantiate a component in behavioral
code. In VHDL we have what are called for-generate schemes so that
makes it easy. is there anything like this in Verilog.
Actually I wanted to create a generic shift register using D flip flop
in structural style, but that doesn't work when I give component
instantiation inside for loop...
Any reply in this regard would be of great help.
Regards,
Sunita.
I have a small Q regarding Verilog.
Since we can't use structural and behavioral styles of modelling
together, is there any method to instantiate a component in behavioral
code. In VHDL we have what are called for-generate schemes so that
makes it easy. is there anything like this in Verilog.
Actually I wanted to create a generic shift register using D flip flop
in structural style, but that doesn't work when I give component
instantiation inside for loop...
Any reply in this regard would be of great help.
Regards,
Sunita.