Basic jitter from a CPLD (XC7500XL)

[Jim]

This is my first design using programmable logic, so apologies if this
question can be found in the datasheet or timing report - I don't know quite
what I'm looking for.

We have a Xilinx XC9572XL (10ns) being driven by either a 12.288MHz or a
6.144MHz clock on the GCK pin. The clock has max jitter 200ps. The CPLD
output is a single flip-flop using this clock, driving a 74HC04 gate (for
buffering).

Is there a way of determining the maximum jitter of the output from the
CPLD? It's for digital audio so this info would be very useful.

Many thanks,

Jim

 

[Austin Lesea]

Jim,

Any question that has the word "jitter" in it is by no means simple, or
even easy, so no apologies required.

Any CMOS circuit must slice the input, and then send it thru the logic,
and pass it back out again.

Programmable logic is no different from any other CMOS device.


At each rising (or falling) edge, common mode noise will change the
switching threshold, and add jitter. To find out how much jitter is
added, one has to measure it.

Measurements of a statistical value requires many millions of cycles to
be captured, and analysed.

There are special software packages, and instruments that do this:

Tektronix scope + jitter software package
LeCroy Jitter Analyser Scopes (software built in)
Agilent DCA's with jitter software packages (built in)
Wavecrest

For the folks who do not have the right equipment, just using infinite
persistence on the scope and triggering on the 1,000th pulse (for
example using time delay) will probably underestimate the peak to peak
jitter by 2 or 3 times!

Peak to peak jitter is all that you really need to know, yet it is
really tough to actually comply with the spec for jitter measurement and
determine the "differences in time of the significant instances of the
signal with respect to a theoretically perfect clock..." from ITU.

If you have a Tek scope, a LeCroy scope, or an Agilent scope, call the
rep, and set up a jitter training session.

Jitter is 'just' phase noise, and like any other noise measurement, is
extremely sensitive to setup. Ground leads, scope bandwidth, signal
integrity (matching) all make it worse, and mask the true jitter added
if you are not careful.

My rule is that I measure jitter, changing and modifying the setup and
instruments until I have measured the smallest value. Until I reach the
smallest value, I have no confidence that I have measured the actual
jitter as if I can measure a smaller number, I still have not taken all
of the other noise factors out of the measurement setup itself!

Oh, and I alwasy make sure I have at least a million clock cycles, and
take repeated samples of a million cycles to be sure that I have the
peak values captured.

Austin

Jim wrote:

This is my first design using programmable logic, so apologies if this
question can be found in the datasheet or timing report - I don't know quite
what I'm looking for.

We have a Xilinx XC9572XL (10ns) being driven by either a 12.288MHz or a
6.144MHz clock on the GCK pin. The clock has max jitter 200ps. The CPLD
output is a single flip-flop using this clock, driving a 74HC04 gate (for
buffering).

Is there a way of determining the maximum jitter of the output from the
CPLD? It's for digital audio so this info would be very useful.

Many thanks,

Jim

 

[Jim]

"Austin Lesea" <austin@xilinx.com> wrote in message
news:c1ig0l$9nl1@cliff.xsj.xilinx.com...

Jim,

Any question that has the word "jitter" in it is by no means simple, or
even easy, so no apologies required.

Any CMOS circuit must slice the input, and then send it thru the logic,
and pass it back out again.

Programmable logic is no different from any other CMOS device.


At each rising (or falling) edge, common mode noise will change the
switching threshold, and add jitter. To find out how much jitter is
added, one has to measure it.

Measurements of a statistical value requires many millions of cycles to
be captured, and analysed.

There are special software packages, and instruments that do this:
snip

Many thanks, Austin, for such a detailed reply.

I never appreciated there was so much to it (for my sins coming mainly from
a software background). Yes I realise now that it is dependent on each
rising and falling edge and so depends on a lot more than the spec of the
CPLD.

I do have a small Tek TDS-220 digital storage scope, but I can see I would
be unlikely to acheive worthwhile results without training and/or other
equipment, and a lot of time.

TBH, the information is partly for our marketing; jitter on a digital audio
(SPDIF) signal is a big issue to many using mid/high-end audio gear,
although TBH I am not sure if some of this is snake oil... However, since
our product processes and then reclocks the stream, it would be useful to
know what the resultant jitter is.

Thanks again Austin,

Jim

 

[Austin Lesea]

Jim,

You are welcome.

Audio is all snake oil, so I have to agree that you need to have a good
story, backed up by some great data, or else the snake oil will taste
all wrong....

It is amazing how sensitive the ear-brain is. Jitter on audio, delay of
audio can easily be discerned.

For example, if you play mp3 files on a computer, any time the song is
affected by a more important interrupt (whoch may only cause a very tiny
time delay of the program material) my brain screams: ARTIFACT!!!!

Gallileo timed his experiments (like the dropping of objects from a
building) by singing a song which had 32nd notes. He was able to
measure differences in arrival times of 1/64 seconds by ear, and time
intervals of about 5 to 10 seconds to an accuracy of 1/32 of a second.

Not bad for just some "wetware."

Austin

Jim wrote:

"Austin Lesea" <austin@xilinx.com> wrote in message
news:c1ig0l$9nl1@cliff.xsj.xilinx.com...

Jim,

Any question that has the word "jitter" in it is by no means simple, or
even easy, so no apologies required.

Any CMOS circuit must slice the input, and then send it thru the logic,
and pass it back out again.

Programmable logic is no different from any other CMOS device.


At each rising (or falling) edge, common mode noise will change the
switching threshold, and add jitter. To find out how much jitter is
added, one has to measure it.

Measurements of a statistical value requires many millions of cycles to
be captured, and analysed.

There are special software packages, and instruments that do this:

snip

Many thanks, Austin, for such a detailed reply.

I never appreciated there was so much to it (for my sins coming mainly from
a software background). Yes I realise now that it is dependent on each
rising and falling edge and so depends on a lot more than the spec of the
CPLD.

I do have a small Tek TDS-220 digital storage scope, but I can see I would
be unlikely to acheive worthwhile results without training and/or other
equipment, and a lot of time.

TBH, the information is partly for our marketing; jitter on a digital audio
(SPDIF) signal is a big issue to many using mid/high-end audio gear,
although TBH I am not sure if some of this is snake oil... However, since
our product processes and then reclocks the stream, it would be useful to
know what the resultant jitter is.

Thanks again Austin,

Jim

 

[Ray Andraka]

I suspect as long as you adhere to good design practices (proper bypassing,
good clock crystal, proper power supplies and distribution), that your jitter
is going to be well under what would affect audio. How much jitter is too
much?

Jim wrote:

"Austin Lesea" <austin@xilinx.com> wrote in message
news:c1ig0l$9nl1@cliff.xsj.xilinx.com...
Jim,

Any question that has the word "jitter" in it is by no means simple, or
even easy, so no apologies required.

Any CMOS circuit must slice the input, and then send it thru the logic,
and pass it back out again.

Programmable logic is no different from any other CMOS device.


At each rising (or falling) edge, common mode noise will change the
switching threshold, and add jitter. To find out how much jitter is
added, one has to measure it.

Measurements of a statistical value requires many millions of cycles to
be captured, and analysed.

There are special software packages, and instruments that do this:
snip

Many thanks, Austin, for such a detailed reply.

I never appreciated there was so much to it (for my sins coming mainly from
a software background). Yes I realise now that it is dependent on each
rising and falling edge and so depends on a lot more than the spec of the
CPLD.

I do have a small Tek TDS-220 digital storage scope, but I can see I would
be unlikely to acheive worthwhile results without training and/or other
equipment, and a lot of time.

TBH, the information is partly for our marketing; jitter on a digital audio
(SPDIF) signal is a big issue to many using mid/high-end audio gear,
although TBH I am not sure if some of this is snake oil... However, since
our product processes and then reclocks the stream, it would be useful to
know what the resultant jitter is.

Thanks again Austin,

Jim

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759

 

[Jim]

"Austin Lesea" <austin@xilinx.com> wrote in message
news:c1ik9m$72t1@cliff.xsj.xilinx.com...

Jim,

You are welcome.

Audio is all snake oil, so I have to agree that you need to have a good
story, backed up by some great data, or else the snake oil will taste
all wrong....

It is amazing how sensitive the ear-brain is. Jitter on audio, delay of
audio can easily be discerned.

For example, if you play mp3 files on a computer, any time the song is
affected by a more important interrupt (whoch may only cause a very tiny
time delay of the program material) my brain screams: ARTIFACT!!!!

Gallileo timed his experiments (like the dropping of objects from a
building) by singing a song which had 32nd notes. He was able to
measure differences in arrival times of 1/64 seconds by ear, and time
intervals of about 5 to 10 seconds to an accuracy of 1/32 of a second.

Not bad for just some "wetware."

Austin

snip

That's a great tale, Austin!

As an aside, in the UK/Europe a movie on a DVD plays at 4% over the speed it
was recorded (due to the 25 frames per second playback compared with the 24
fps film rate). The audio is therefore 4% sharper, I understand. Most people
(including myself) don't notice this, but for those who are tonally acute it
makes the listening experience less than ideal.

Jim

 

[Jim]

"Ray Andraka" <ray@andraka.com> wrote in message
news:403CD7E4.C2A23732@andraka.com...

I suspect as long as you adhere to good design practices (proper
bypassing,
good clock crystal, proper power supplies and distribution), that your
jitter
is going to be well under what would affect audio. How much jitter is too
much?

snip

Hi Ray,

Thanks for the advice. We will try to follow good design practices as you
say.

From what I have gleaned from the web, 300ps or so of jitter will have no
effect on a SPDIF signal with a 48kHz sample rate (serial bit rate of
6.144MHz). However, there are "dejitter" boxes around that advertise 75ps or
better (and sell for $$$$!) To me this sounds OTT, since I understand that
the PLL in the receiver IC of the amplifier will change the jitter (for
better or worse) anyway, regardless of the jitter on the incoming signal.

FWIW our product is not being sold to reduce jitter but since it reclocks
the data we need some understanding of its effect on the bitstream. We were
hoping to quote 200ps, since that is the typical jitter from the clock we
are using, and it seems to be recognised as an acceptable level for most
applications. I can now see that to find out what it actual is would not be
so easy.

Jim

 

[Philip Freidin]

On Wed, 25 Feb 2004 13:06:30 -0000, "Jim" <jim@nospam.com> wrote:

This is my first design using programmable logic, so apologies if this
question can be found in the datasheet or timing report - I don't know quite
what I'm looking for.

We have a Xilinx XC9572XL (10ns) being driven by either a 12.288MHz or a
6.144MHz clock on the GCK pin. The clock has max jitter 200ps. The CPLD
output is a single flip-flop using this clock, driving a 74HC04 gate (for
buffering).

Is there a way of determining the maximum jitter of the output from the
CPLD? It's for digital audio so this info would be very useful.

Many thanks,

Jim

As your signal moves through each stage of your design, each net and
gate can contribute some jitter. I suspect that the combined jitter
probably has a distribution related to the square root of the sum of
the squares of the separate jitter components. The peak may be as high
as the sum of the non mutually exclusive jitter components.

Since you are reclocking your data on the output of the CPLD, all the
stuff going on inside the CPLD is probably irrelevant, except for its
noise contribution to the Tco of the final flip flop. This is because
the clock has to come into the CPLD (input level sense is modified by
on chip noise), has to traverse the CPLD (unknown number of rebuffering
stages, each with level sense modified by the on-chip noise), and then
the output flip flop has to use this clock. Clearly the jitter can be
no less than the initial 200ps of your clock, but could be more. I have
no supportable idea of how much "more" means. If I was a guessing dude,
and rather pessimistic, maybe 200ps to 400ps of additional jitter?

Jitter can be attenuated by using a PLL on the clock, but it has to be
a PLL designed specifically for jitter attenuation.

If your goal was to have sub 200ps final jitter, I would suggest
researching a structure such as:

Take the output of the CPLD and run it through a single FF outside the
CPLD, such as a NL17SZ74US .

Use extraordinary efforts for isolation from noise, such as sepparate
local low noise LDO regulator with local bypassing for its power supply
and appropriate issolation from ground noise of the rest of the system.

Take your clock and pass it through a jitter attenuation PLL, with
similar care with power supply and grounds. Use this (improved) clock
for this external retiming flip flop.

Measuring actual jitter parameters is non-trivial. There are some
outrageously expensive scopes and analyzers available that are designed
specifically for these types of measurements. Normal (very fast) scopes
can be used, but they can contribute significantly to the measured
jitter because of their inherent jitter in their trigger circuit and
their horizontal time base oscillator. An alternative is to use a
spectrum analyzer. With enough math, you can turn the results into
jitter numbers, for some but not all jitter parameters.

Good luck,

Philip


Philip Freidin
Fliptronics

 

[Jim]

"Philip Freidin" <philip@fliptronics.com> wrote in message
news:10tp309nnr65be5n29ei4q30sdf7s93p84@4ax.com...
<snip>

If your goal was to have sub 200ps final jitter, I would suggest
researching a structure such as:

Take the output of the CPLD and run it through a single FF outside the
CPLD, such as a NL17SZ74US .

Use extraordinary efforts for isolation from noise, such as sepparate
local low noise LDO regulator with local bypassing for its power supply
and appropriate issolation from ground noise of the rest of the system.

Take your clock and pass it through a jitter attenuation PLL, with
similar care with power supply and grounds. Use this (improved) clock
for this external retiming flip flop.

Measuring actual jitter parameters is non-trivial. There are some
outrageously expensive scopes and analyzers available that are designed
specifically for these types of measurements. Normal (very fast) scopes
can be used, but they can contribute significantly to the measured
jitter because of their inherent jitter in their trigger circuit and
their horizontal time base oscillator. An alternative is to use a
spectrum analyzer. With enough math, you can turn the results into
jitter numbers, for some but not all jitter parameters.

Good luck,

Philip


Philip Freidin
Fliptronics

Thank you Philip for your very thorough reply. I can see that minimizing
jitter and measuring jitter are deep subjects in themselves. Your ideas seem
very sensible and I would love to try out that route. TBH, I don't have the
time or knowledge to pursue it as much as maybe it deserves. Since our
product is not being sold to reduce jitter, I am hoping that by keeping it
simple and using good design pratices the jitter will be within acceptable
limits - I've just seen some audio magazine "lab" reports on various DVD
players, and they seem to go up to 500ps (with an average of about 350ps).

FYI our clock is the PLL in a Cirrus Logic CS8416 digital audio receiver IC,
with a max jitter of 200ps. We use that as it needs to handle the various
frequencies associated with digital audio. I don't know if anyone uses it to
de-jitter audio signals.

As long as our product does not make the jitter unacceptable we are going to
probably have to go with that - it's a low price product. The prototype
"sounds" fine to me(!), i.e. it sounds no different to when the product is
not there. I haven't done any jitter measurements on it, and unfortunately I
don't think my scope, or I, are up to it.

Jim

 

[Jim Granville]

Jim wrote:

This is my first design using programmable logic, so apologies if this
question can be found in the datasheet or timing report - I don't know quite
what I'm looking for.

We have a Xilinx XC9572XL (10ns) being driven by either a 12.288MHz or a
6.144MHz clock on the GCK pin. The clock has max jitter 200ps. The CPLD
output is a single flip-flop using this clock, driving a 74HC04 gate (for
buffering).

Is there a way of determining the maximum jitter of the output from the
CPLD? It's for digital audio so this info would be very useful.

You can get a feel for jitter, and what matters, by doing some
slew/threshold calculations.
eg consider a clock signal slewing at 1Volt/ns, and apply 10mv of
threshold noise ( combined effects of Vcc noise ,Gnd bounce and
crosstalk ) then purely the threshold modulation gives 10ps of jitter.
So, in CMOS a clean (linear) low noise power supply will help,
as will short, shielded traces for Osc module -> PLD.
Faster edges from the Osc module will help (if you get the choice),
and keeping any async, or random content signals 'away' from the clock
divider portion of the PLD.
If you have a PLD+HC04, doing only /2, you could consider a HC1G79
which is a tiny logic FF, to do both jobs. With NO other signals,
and very low power, as well as a tiny package, this should have the
lowest possible jitter.

In Audio, I believe jitter affects absolute noise floors, so you could
look for that effect.
At 48KHz that's ~20us, so 20ns jitter is -60dB, and 20ps jitter
is -120dB (numeric ratio only) - so it's not entirely snake
oil, jitter numbers well under 1ns could have a measurable (if not
audible impact.

For some real values quoted by process, see OnSemi's TND301
http://www.onsemi.com/pub/Collateral/TND301-D.PDF

-jg

 

[Jim]

"Jim Granville" <no.spam@designtools.co.nz> wrote in message
news:Le8%b.28417$ws.3197913@news02.tsnz.net...
<snip>

You can get a feel for jitter, and what matters, by doing some
slew/threshold calculations.
eg consider a clock signal slewing at 1Volt/ns, and apply 10mv of
threshold noise ( combined effects of Vcc noise ,Gnd bounce and
crosstalk ) then purely the threshold modulation gives 10ps of jitter.
So, in CMOS a clean (linear) low noise power supply will help,
as will short, shielded traces for Osc module -> PLD.
Faster edges from the Osc module will help (if you get the choice),
and keeping any async, or random content signals 'away' from the clock
divider portion of the PLD.
If you have a PLD+HC04, doing only /2, you could consider a HC1G79
which is a tiny logic FF, to do both jobs. With NO other signals,
and very low power, as well as a tiny package, this should have the
lowest possible jitter.

In Audio, I believe jitter affects absolute noise floors, so you could
look for that effect.
At 48KHz that's ~20us, so 20ns jitter is -60dB, and 20ps jitter
is -120dB (numeric ratio only) - so it's not entirely snake
oil, jitter numbers well under 1ns could have a measurable (if not
audible impact.

For some real values quoted by process, see OnSemi's TND301
http://www.onsemi.com/pub/Collateral/TND301-D.PDF

-jg

Thanks Jim for your feedback. I will try to do some calculations as you
suggest, at least to know what ballpark we are likely to be in! That OnSemi
document looks very useful - I will read it properly as soon as I get a
moment.

I'm not quite sure what you mean about the HC1G79. To give you more info,
the CPLD buffers and proceses the digitial bitstream with the help of some
SRAM and other ICs and then spits it out. The output is then buffered via a
NOT gate to parallel NOT gates of the HC04 to provide enough drive for a
pulse transformer (I now realise I should have mentioned the gates and the
pulse transformer in the beginning, as they could also have a significant
effect on jitter - I was more concerned about the CPLD initially). I've
googled for HC1G79 but to no avail so far.

Jim

 

[Jim Granville]

Jim wrote:

Thanks Jim for your feedback. I will try to do some calculations as you
suggest, at least to know what ballpark we are likely to be in! That OnSemi
document looks very useful - I will read it properly as soon as I get a
moment.

I'm not quite sure what you mean about the HC1G79. To give you more info,
the CPLD buffers and proceses the digitial bitstream with the help of some
SRAM and other ICs and then spits it out. The output is then buffered via a
NOT gate to parallel NOT gates of the HC04 to provide enough drive for a
pulse transformer (I now realise I should have mentioned the gates and the
pulse transformer in the beginning, as they could also have a significant
effect on jitter - I was more concerned about the CPLD initially).

When you use the slew model, you can appreciate any pulse transformer (
with its slow slew rates ) will likely have a big effect on jitter.

Why is the transformer there, and do you work on both sides of it
- ie is the RX side your design ? Some care will be needed there,
to both keep Tsu/Th ok, and to minimise clock path degrade.

I've googled for HC1G79 but to no avail so far.

http://www.philipslogic.com/products/picogate/flipflops/

-jg

 

[Jim]

"Jim Granville" <no.spam@designtools.co.nz> wrote in message
news2t%b.28542$ws.3212062@news02.tsnz.net...

When you use the slew model, you can appreciate any pulse transformer (
with its slow slew rates ) will likely have a big effect on jitter.

Why is the transformer there, and do you work on both sides of it
- ie is the RX side your design ? Some care will be needed there,
to both keep Tsu/Th ok, and to minimise clock path degrade.

I've googled for HC1G79 but to no avail so far.

http://www.philipslogic.com/products/picogate/flipflops/

-jg

Thank you for the link Jim.

I do see what you mean about the slew rate of the transformer and its effect
on jitter. We are using a pulse transformer in the transmit side only. This
is to achieve galvanic isolation and is recommend for SPDIF output circuits
in the datasheets and documents we have, e.g.:
http://www.cirrus.com/en/pubs/proDatasheet/CS8405A-f.pdf (800KB) page 34 -
consumer output circuit
http://www.cirrus.com/en/pubs/appNote/AN134-4.pdf (70KB)
http://www.epanorama.net/documents/audio/spdif.html (a collection of SPDIF
circuits from various sources)

The transformer is a Pulse Engineering PE-65812 and is recommended by Cirrus
Logic for SPDIF transmission. Hopefully this means jitter from the
transformer is kept as low as possible. Since the SPDIF outputs of all
consumer devices are meant to have a transformer in them (AFAIK), then they
must all have this problem?

On the other hand, I have also seen that many DIY audio geeks prefer a
direct connection with no transformer, I guess for exactly the reasons you
have suggested. However, since our product is for sale to the general
public, I like the idea of galvanic isolation to cover us in case of
incorrect connections by users and also failure within the unit itself that
could possibly damage their expensive equipment.

Jim

 

[Jim Granville]

I do see what you mean about the slew rate of the transformer and its effect
on jitter. We are using a pulse transformer in the transmit side only. This
is to achieve galvanic isolation and is recommend for SPDIF output circuits
in the datasheets and documents we have, e.g.:
http://www.cirrus.com/en/pubs/proDatasheet/CS8405A-f.pdf (800KB) page 34 -
consumer output circuit
http://www.cirrus.com/en/pubs/appNote/AN134-4.pdf (70KB)
http://www.epanorama.net/documents/audio/spdif.html (a collection of SPDIF
circuits from various sources)

The transformer is a Pulse Engineering PE-65812 and is recommended by Cirrus
Logic for SPDIF transmission. Hopefully this means jitter from the
transformer is kept as low as possible. Since the SPDIF outputs of all
consumer devices are meant to have a transformer in them (AFAIK), then they
must all have this problem?

On the other hand, I have also seen that many DIY audio geeks prefer a
direct connection with no transformer, I guess for exactly the reasons you
have suggested. However, since our product is for sale to the general
public, I like the idea of galvanic isolation to cover us in case of
incorrect connections by users and also failure within the unit itself that
could possibly damage their expensive equipment.

This mentions Biphase modulation, and that requires clock recovery on
the RX side. Thus you should choose low jitter Xtal source, (and a high
accuracy one could also help, if a digital PLL is used in the RX ) but
the jitter introduced by the cpld will likely be insignifcant.
I see the cirrus device specs MAX of 1ns jitter, which may or may not
include the transformer

The RX clock recovery will lock into the centres of the data bi-phase
bits, so final clock jitter will be determined mainly by their lock scheme.
Of course, poor jitter, or frequency skew, on the data edges makes the
clock lock job harder...
-jg

 

[Christoph Brinkhaus]

Hi Philip!

Philip Freidin <philip@fliptronics.com> wrote:

On Wed, 25 Feb 2004 13:06:30 -0000, "Jim" <jim@nospam.com> wrote:

Is there a way of determining the maximum jitter of the output from the
CPLD? It's for digital audio so this info would be very useful.

Many thanks,

Jim

Jitter can be attenuated by using a PLL on the clock, but it has to be
a PLL designed specifically for jitter attenuation.

Shouldnt it be possible to use a LC band pass filter (or even a crystal
filter) to remove spectral components far from the clock frequency?
This should improve at least the peak/rms ratio.
I am not sure if my idea is not too stupid.
PLL design has also some difficulties.

If your goal was to have sub 200ps final jitter, I would suggest
researching a structure such as:

Take the output of the CPLD and run it through a single FF outside the
CPLD, such as a NL17SZ74US .

For analogue filter a limiter amplifier or so is also necessary to

convert the filtered signal back to the "digital domain".

Use extraordinary efforts for isolation from noise, such as sepparate
local low noise LDO regulator with local bypassing for its power supply
and appropriate issolation from ground noise of the rest of the system.

This is always a good idea, for analogue and digital circuits as well.

In my experinence the influence of the power supply is often underestimated.
Especially when there some lack of time....

Take your clock and pass it through a jitter attenuation PLL, with
similar care with power supply and grounds. Use this (improved) clock
for this external retiming flip flop.

Best regards,

Christoph

Good luck,

Philip


Philip Freidin
Fliptronics

 

[Jim]

"Jim Granville" <no.spam@designtools.co.nz> wrote in message
news:yvu%b.28550$ws.3214332@news02.tsnz.net...

I do see what you mean about the slew rate of the transformer and its
effect
on jitter. We are using a pulse transformer in the transmit side only.
This
is to achieve galvanic isolation and is recommend for SPDIF output
circuits
in the datasheets and documents we have, e.g.:
http://www.cirrus.com/en/pubs/proDatasheet/CS8405A-f.pdf (800KB) page
34 -
consumer output circuit
http://www.cirrus.com/en/pubs/appNote/AN134-4.pdf (70KB)
http://www.epanorama.net/documents/audio/spdif.html (a collection of
SPDIF
circuits from various sources)

The transformer is a Pulse Engineering PE-65812 and is recommended by
Cirrus
Logic for SPDIF transmission. Hopefully this means jitter from the
transformer is kept as low as possible. Since the SPDIF outputs of all
consumer devices are meant to have a transformer in them (AFAIK), then
they
must all have this problem?

On the other hand, I have also seen that many DIY audio geeks prefer a
direct connection with no transformer, I guess for exactly the reasons
you
have suggested. However, since our product is for sale to the general
public, I like the idea of galvanic isolation to cover us in case of
incorrect connections by users and also failure within the unit itself
that
could possibly damage their expensive equipment.

This mentions Biphase modulation, and that requires clock recovery on
the RX side. Thus you should choose low jitter Xtal source, (and a high
accuracy one could also help, if a digital PLL is used in the RX ) but
the jitter introduced by the cpld will likely be insignifcant.
I see the cirrus device specs MAX of 1ns jitter, which may or may not
include the transformer

The RX clock recovery will lock into the centres of the data bi-phase
bits, so final clock jitter will be determined mainly by their lock scheme
..
Of course, poor jitter, or frequency skew, on the data edges makes the
clock lock job harder...
-jg

In fact for the RX side I am using a Cirrus Logic digital audio receiver IC
with in-built PLL, CS8416:
http://www.cirrus.com/en/products/pro/detail/P1005.html
It talks about low-jitter clock recovery. I am using the recovered clock
from this IC to clock the CPLD. I was thinking I could maybe add another
CS8416 and a flipflop to reclock the CPLD's output before routing it through
the transformer, but didn't want to if not necessary (cost & extra
components & something else to worry about!)

-Jim