base-x 6.3 RAM problem

Hello,


I am trying very hard to get a RAM into my mostly state machine based
design. Coregen has given me a 32bit x 8kb ram (this is for a spartan
3) single port memory just fine. However, when I look at the RTL
schematic generated by XST (this is version 6.3.03 of xilinx basex)
the din, dout, and addr are not connected even though they clearly are
in my vhdl code. Like I said my design is mostly a few state machines,
a master controller state machine and 2 counters for incrementing the
ram. When I go to the synthesis step I get these messages:


WARNING:HDLParsers:3481 - No primary, secondary unit in the file
C:\VHDL_Code\v0.0.6_TEST_NEW_RAM\D64USB_Pattern_Generator/ram32x8k.vhd.
Ignore this file from project file control_top_vhdl.prj.
Compiling vhdl file
C:/v0.0.6_TEST_NEW_RAM/D64USB_Pattern_Generator/controller.vhd in
Library work.

WARNING:Xst:766 -
C:/v0.0.6_TEST_NEW_RAM/D64USB_Pattern_Generator/control_top.vhd line
282: Generating a Black Box for component <ram32x8k>.
Entity <control_top> analyzed. Unit <control_top> generated.


WARNING:Xst:1291 - FF/Latch <WR_DAC_CNT0_count_v_4> is unconnected in
block <control_top>.
WARNING:Xst:1291 - FF/Latch <WR_DAC_CNT0_count_v_5> is unconnected in
block <control_top>.
WARNING:Xst:1291 - FF/Latch <WR_DAC_CNT0_count_v_6> is unconnected in
block <control_top>.
WARNING:Xst:1291 - FF/Latch <WR_DAC_CNT0_count_v_7> is unconnected in
block <control_top>.
WARNING:Xst:1291 - FF/Latch <WR_DAC_CNT0_count_v_8> is unconnected in
block <control_top>.
WARNING:Xst:1291 - FF/Latch <WR_DAC_CNT0_count_v_9> is unconnected in
block <control_top>.
WARNING:Xst:1291 - FF/Latch <WR_DAC_CNT0_count_v_10> is unconnected in
block <control_top>.
WARNING:Xst:1291 - FF/Latch <WR_DAC_CNT0_count_v_11> is unconnected in
block <control_top>.


The first two warnings are what I think is going wrong, for some
reason the RAM isn't being included in my design, but I don't
understand why since it seems to be working properly in the
pre-synthesis simulation. Anyone encountered anything like this before
? Those aren't all the warnings though, just a representative sample.

thanks,
Don

 

[Mike Treseler]

fenriswolfnews@hotmail.com wrote:

the RAM isn't being included in my design, but I don't
understand why since it seems to be working properly in the
pre-synthesis simulation. Anyone encountered anything like this before

Yes. That is one reason why I infer ram
from a vhdl synthesis template
instead of using vendor specific core generators.
This makes simulation easier and faster also.

-- Mike Treseler

 

can you show me how you infer the ram perhaps ? It's annoying that they
don't show the connections. I went back to an old design of mine that I
know works and the RAM was similarly unconnected in the RTL diagram. I
found my problem anyway, I had a load counter line that was NOT
necessary for the logic simulation to work, but was necessary for the
counter to get synthesized properly. This same counter was hooked to my
RAM address input, which was what was throwing me since the address bus
was showing up (among other things) unconnected in the RTL schematic
display under XST synthesis options.

 

[Mike Treseler]

fenriswolfnews@hotmail.com wrote:

can you show me how you infer the ram perhaps ?

Search the vendor app notes or see
http://groups.google.com/groups?q=vhdl+entity+sync_ram

-- Mike Treseler

 

Mike Treseler wrote:

fenriswolfnews@hotmail.com wrote:
can you show me how you infer the ram perhaps ?

Search the vendor app notes or see
http://groups.google.com/groups?q=vhdl+entity+sync_ram

-- Mike Treseler

thanks for your help. I am posting my solution given your guidance I
found an instantiation vhdl module for synplify. I had to change it for
Spartan 3 just a little. Basically I moved the output to inside the
rising_edge(clk) if conditional statement. The original was outside for
some reason. if you do that then it wants to use a ton of extra slices
on the fpga. Anyway this seems to be a decent way to instatiate block
ram. This was done under XST, but probably works for other synthesis
tools that aren't so free .


--- begin code --
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity ram32x8 is
generic(d_width : integer := 32;
addr_width : integer := 13;
mem_depth : integer := 8000);
port(o : out std_logic_vector(d_width - 1 downto 0);
we, wclk, en: in std_logic;
d: in std_logic_vector(d_width - 1 downto 0);
addr : in std_logic_vector(addr_width - 1 downto 0));
end ram32x8;

architecture Behavioral of ram32x8 is
type mem_type is array(mem_depth - 1 downto 0) of
std_logic_vector(d_width - 1 downto 0);
signal mem : mem_type;
begin
process(wclk, we, en, addr)
begin
if rising_edge(wclk) then
if en = '1' then
if we = '1' then
mem(conv_integer(addr)) <= d;
else
o <= mem(conv_integer(addr));
end if;
end if;
end if;
end process;

--o <= mem(conv_integer(addr));

end Behavioral;
-- end code --