Barrel shifter compilation in QuartusII

[ALuPin]

Hi,

I tried to compile the code presented some days ago in this newsgroup.
I use Altera QuartusII v3.0 SP2

and got the following warning:

Warning: VHDL Subtype or Type Declaration warning at
numeric_std.vhd(878):
subtype or type has null range Switching left and right bound of
range.

Was does that mean?


Apart from that I get the Info
"No valid register-to-register paths exist for clock Clk"

What does go wrong with timing calculation?

Rgds


library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity barrelshifter is
port( Quantity : in unsigned(31 downto 0);
Amount : in unsigned(4 downto 0);
Reset : in std_logic;
Clk : in std_logic;
Output : out std_logic_vector(31 downto 0)
);
end barrelshifter;

architecture ro_lft of barrelshifter is
signal rotated : std_logic_vector(31 downto 0);
signal rotate_by : unsigned(4 downto 0);

begin
rotate_by <= Amount;

process (Clk)
begin
if Reset='1' then
rotated <= (others => '0');
elsif clk = '1' and clk'event then
rotated <= std_logic_vector(shift_right(quantity,to_integer(unsigned(rotate_by))));
end if;
end process;

Output <= rotated;

end ro_lft;