barrel shifter 2

[Hendrik Greving]

hi,

does anybody know where to obtain the algorithm of how to make a
synthesis of a constant barrel shifter, or knows a paper that deals with
this issue?

e.g. result = 00011101 << b

is optimized by combining the b input bits for the output "result"
instead of using multiplexers.

Regards,
Hendrik Greving

 

[Mike Treseler]

Hendrik Greving wrote:

does anybody know where to obtain the algorithm of how to make a
synthesis of a constant barrel shifter

http://groups.google.com/groups?q=barrel+shifter+vhdl+OR+verilog

 

[Hendrik Greving]

Mike Treseler wrote:

Hendrik Greving wrote:

does anybody know where to obtain the algorithm of how to make a
synthesis of a constant barrel shifter


http://groups.google.com/groups?q=barrel+shifter+vhdl+OR+verilog

Maybe you didn't understand the question. It was targeted on how to make
the optimizations for a constant barrel shifter.

Regards,
Hendrik

 

[Mike Treseler]

Hendrik Greving wrote:

Maybe you didn't understand the question. It was targeted on how to make
the optimizations for a constant barrel shifter.

Sorry.
I don't write synthesis software.
I use it.
However, you can learn a lot about it
by running some code through and
viewing the rtl schematic.
Change constraints. Repeat.

-- Mike Treseler

 

[Hendrik Greving]

Mike Treseler wrote:

Hendrik Greving wrote:

Maybe you didn't understand the question. It was targeted on how to make
the optimizations for a constant barrel shifter.


Sorry.
I don't write synthesis software.
I use it.
However, you can learn a lot about it
by running some code through and
viewing the rtl schematic.
Change constraints. Repeat.

-- Mike Treseler

A cadence guy in the verilog newsgroup gave an excellent answer. It's a
problem of simplifying the combinational truth table of the signal
sequences of each output bit that give 1 and of the b input.

Hendrik