bandwidth and fifo depth

[anon]

i have following scenario, looking to see what the optimal fifo depth is.

input to an interface is runnin @200MHz and 4 bytes written every clock.
data is read out of the interface @200MHz but 8 bytes is read at a time.

input BW is 800Mbits/sec, output is 1600Mbits/sec. , but there can be back pressure on the read side.

What is required in terms on info to calculate fifo depth?

 

[Gabor]

On 6/30/2015 4:24 PM, anon wrote:

i have following scenario, looking to see what the optimal fifo depth is.

input to an interface is runnin @200MHz and 4 bytes written every clock.
data is read out of the interface @200MHz but 8 bytes is read at a time.

input BW is 800Mbits/sec, output is 1600Mbits/sec. , but there can be back pressure on the read side.

What is required in terms on info to calculate fifo depth?

It sounds like when there's no back-pressure the FIFO will be almost
empty all the time. So you really need to know how long the back
pressure can be applied and multiply that by the input bandwidth
to get a rough estimate. Then remember that if the back-pressure
could also be re-applied before the FIFO runs down to almost empty
again, you need to take that into consideration, too.

I'd say you really want to know the mechanism that causes the
back-pressure, for example a shared bus being temporarily used
by another system resource, or just a destination data sink that
has some other constant bandwidth limit. Also is the input data
continuous or bursty? Basically you need a system-level approach
to this and the more accurately you can model the system behavior
the better you can predict the depth requirement. Without
sufficient modeling, you may need to add depth to cover the
uncertainty.

--
Gabor

 

[Michael Kellett]

Gabor:

On 6/30/2015 4:24 PM, anon wrote:
i have following scenario, looking to see what the optimal fifo depth
is.

input to an interface is runnin @200MHz and 4 bytes written every
clock.
data is read out of the interface @200MHz but 8 bytes is read at a
time.

input BW is 800Mbits/sec, output is 1600Mbits/sec. , but there can be
back pressure on the read side.

What is required in terms on info to calculate fifo depth?


It sounds like when there's no back-pressure the FIFO will be almost
empty all the time. So you really need to know how long the back
pressure can be applied and multiply that by the input bandwidth
to get a rough estimate. Then remember that if the back-pressure
could also be re-applied before the FIFO runs down to almost empty
again, you need to take that into consideration, too.

All that and ....

once you have a rough estimate you may well find that (in FPGAs) your
fifo is going to be much smaller than a block RAM but too big to put in
general fabric in which case you don't need to refine the estimate that
much. If you are using a lot of resource for the FIFO there may be a
need to pin things down very precisely - I think these things more often
tend to be expressed in orders of magnitude (decimal or binary). It
won't matter if the optimum FIFO is 400 or 407 words, this issue is more
often between 256 and512.
Remember Veriliog is an HDL - never forget the hardware.

Michael Kellett

I'd say you really want to know the mechanism that causes the
back-pressure, for example a shared bus being temporarily used
by another system resource, or just a destination data sink that
has some other constant bandwidth limit. Also is the input data
continuous or bursty? Basically you need a system-level approach
to this and the more accurately you can model the system behavior
the better you can predict the depth requirement. Without
sufficient modeling, you may need to add depth to cover the
uncertainty.

--
Gabor