Bad array access?

[Martin Vass]

This code compiles without errors on 2 simulators and produces the
output "a[2] is 1".

What's going on? Shouldn't this be flagged as a syntax error?

TIA

-MV

------

module top;
initial
test;
task test;
integer a;
begin
a[0] = 1;
a[1] = 2;
a[2] = 3;
$display("a[2] is %d", a[2]);
end
endtask
endmodule

 

[Jerome]

A is an integer.
A[2] is the bit 2 of A.
A[2] = 3, set this bit to 1.
It is correct.
but if you define A as an array:
reg [15:0] A[15:0];

you will have the "expected" display.



Martin Vass a écrit :

This code compiles without errors on 2 simulators and produces the
output "a[2] is 1".

What's going on? Shouldn't this be flagged as a syntax error?

TIA

-MV

------

module top;
initial
test;
task test;
integer a;
begin
a[0] = 1;
a[1] = 2;
a[2] = 3;
$display("a[2] is %d", a[2]);
end
endtask
endmodule

 

[Martin Vass]

On Mon, 19 Feb 2007 18:13:07 +0100, Jerome <jeje@.com> wrote:

A is an integer.
A[2] is the bit 2 of A.
A[2] = 3, set this bit to 1.
It is correct.
but if you define A as an array:
reg [15:0] A[15:0];

you will have the "expected" display.

So... an integer is actually a vector? What's the point of integers?
Is 'integer' just another name for a signed reg? And how big is an
integer? Palnitkar doesn't appear to answer any of these questions. I
can't even find 'bit select' or 'part select' in the index...

Thanks

-MV

 

[Stephen Williams]

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Martin Vass wrote:

On Mon, 19 Feb 2007 18:13:07 +0100, Jerome <jeje@.com> wrote:

A is an integer.
A[2] is the bit 2 of A.
A[2] = 3, set this bit to 1.
It is correct.
but if you define A as an array:
reg [15:0] A[15:0];

you will have the "expected" display.

So... an integer is actually a vector? What's the point of integers?
Is 'integer' just another name for a signed reg? And how big is an
integer? Palnitkar doesn't appear to answer any of these questions. I
can't even find 'bit select' or 'part select' in the index...

integer foo;

is exactly the same as

reg signed [N-1:0] foo;

where N is unspecified but >= 32. Integers in Verilog do not have
predefined sizes, instead leaving their width to the compiler to
decide.


- --
Steve Williams "The woods are lovely, dark and deep.
steve at icarus.com But I have promises to keep,
http://www.icarus.com and lines to code before I sleep,
http://www.picturel.com And lines to code before I sleep."
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[Kevin Neilson]

Martin Vass wrote:

So... an integer is actually a vector? What's the point of integers?
Is 'integer' just another name for a signed reg? And how big is an
integer? Palnitkar doesn't appear to answer any of these questions. I
can't even find 'bit select' or 'part select' in the index...

Thanks

-MV

Palnitkar? Don't get me started. You can use this syntax, though,
which is only different from your code as shown by my comment:

module top;
initial
test;
task test;
integer a [2:0]; //*** Kevin added '[2:0]' ***
begin
a[0] = 1;
a[1] = 2;
a[2] = 3;
$display("a[2] is %d", a[2]);
end
endtask
endmodule

This gives you an array of integers. Before, you were indexing the
individual bits of a single integer. You can still access the bits of
the integer in the array with a double index. For example, the zeroth
bit of integer 2 is a[2][0]. The 'integer' type might not synthesize as
well as 'reg'.
-Kevin