J
John Kolb
Guest
Instead of a hierarchical series of models as I've successfully tested in the
past, the last netlist I received from our back-end contractor was flattened to
a single level using the VHDL style embedded signal names with backslashes.
When I try to link into internal signals in the ignite module, I'm unable to
find the proper syntax .Trying to simulate it with Modelsim PE 5.7c or 5.7e
either gives compile errors or as below, unresolved errors.
What's the proper syntax? Any suggestions deeply appreciated. -- John
Top level Verilog testbench:
ignite_top ignite_A(
.... );
wire [7:0] OP = {ignite_A.\core/control_a/opc_reg_7.Q ,
ignite_A.\core/control_a/opc_reg_6.Q ,
....
ignite_A.\core/control_a/opc_reg_1.Q ,
ignite_A.\core/control_a/opc_reg_0.Q };
Verilog netlist
module ignite_top(
....
DFFRHQX4 \core/control_a/opc_reg_7 (.CK(clk_424), .D(\core/control_a/n_24512
), .Q(\core/control_a/L [7]), .RN(\u_dval_sync/rstn_reg_11 ));
....
DFFRHQX4 \core/control_a/opc_reg_0 (.CK(clk_424), .D(\core/control_a/n_24470
), .Q(\core/control_a/L [0]), .RN(\u_dval_sync/rstn_reg_132 ));
....
endmodule
# ** Error: (vsim-3043) E:/silterra/sdf/ignite-tb-silterra-flat.v(243):
Unresolved reference to '\core/control_a/opc_reg_7.Q\' in
ignite_A.\core/control_a/opc_reg_7.Q\.
# Region: /ignite_tb
# ** Error: (vsim-3043) E:/silterra/sdf/ignite-tb-silterra-flat.v(244):
Unresolved reference to '\core/control_a/opc_reg_6.Q\' in
ignite_A.\core/control_a/opc_reg_6.Q\.
# Region: /ignite_tb
....
# ** Error: (vsim-3043) E:/silterra/sdf/ignite-tb-silterra-flat.v(249):
Unresolved reference to '\core/control_a/opc_reg_1.Q\' in
ignite_A.\core/control_a/opc_reg_1.Q\.
# Region: /ignite_tb
# ** Error: (vsim-3043) E:/silterra/sdf/ignite-tb-silterra-flat.v(250):
Unresolved reference to '\core/control_a/opc_reg_0.Q\' in
ignite_A.\core/control_a/opc_reg_0.Q\.
# Region: /ignite_tb
past, the last netlist I received from our back-end contractor was flattened to
a single level using the VHDL style embedded signal names with backslashes.
When I try to link into internal signals in the ignite module, I'm unable to
find the proper syntax .Trying to simulate it with Modelsim PE 5.7c or 5.7e
either gives compile errors or as below, unresolved errors.
What's the proper syntax? Any suggestions deeply appreciated. -- John
Top level Verilog testbench:
ignite_top ignite_A(
.... );
wire [7:0] OP = {ignite_A.\core/control_a/opc_reg_7.Q ,
ignite_A.\core/control_a/opc_reg_6.Q ,
....
ignite_A.\core/control_a/opc_reg_1.Q ,
ignite_A.\core/control_a/opc_reg_0.Q };
Verilog netlist
module ignite_top(
....
DFFRHQX4 \core/control_a/opc_reg_7 (.CK(clk_424), .D(\core/control_a/n_24512
), .Q(\core/control_a/L [7]), .RN(\u_dval_sync/rstn_reg_11 ));
....
DFFRHQX4 \core/control_a/opc_reg_0 (.CK(clk_424), .D(\core/control_a/n_24470
), .Q(\core/control_a/L [0]), .RN(\u_dval_sync/rstn_reg_132 ));
....
endmodule
# ** Error: (vsim-3043) E:/silterra/sdf/ignite-tb-silterra-flat.v(243):
Unresolved reference to '\core/control_a/opc_reg_7.Q\' in
ignite_A.\core/control_a/opc_reg_7.Q\.
# Region: /ignite_tb
# ** Error: (vsim-3043) E:/silterra/sdf/ignite-tb-silterra-flat.v(244):
Unresolved reference to '\core/control_a/opc_reg_6.Q\' in
ignite_A.\core/control_a/opc_reg_6.Q\.
# Region: /ignite_tb
....
# ** Error: (vsim-3043) E:/silterra/sdf/ignite-tb-silterra-flat.v(249):
Unresolved reference to '\core/control_a/opc_reg_1.Q\' in
ignite_A.\core/control_a/opc_reg_1.Q\.
# Region: /ignite_tb
# ** Error: (vsim-3043) E:/silterra/sdf/ignite-tb-silterra-flat.v(250):
Unresolved reference to '\core/control_a/opc_reg_0.Q\' in
ignite_A.\core/control_a/opc_reg_0.Q\.
# Region: /ignite_tb