Avoiding races in verification code

[Andrew Mazin]

Hi All,

In my verification module, I am sending packets to the link. To do
this, I am using blocking tasks like this one:

task send_packet;
.....
for (i=0; i< packet_length; i=i+1)
@(posedge clk) output = data;
....

Between packets, my module must send idles, starting immediately after
packet and ending just before the new one.
I can define the register which controls idles generations:

task send_packet;
.....
disable_idles = 1;
for (i=0; i< packet_length; i=i+1)
@(posedge clk) output = data;
disable_idles = 0;
....


Then, I may use "always" construct to generate idles:

always @(posedge clk)
if (disable_idles == 0)
send_idle;

It will work, but races will occur: disable_idles is written and read
at the same simulation time.

My model must be also able to send packets back-to-back, without idles
between packets.

Is there a way to write this function race-free?
Any help will be highly appreciated

Thanks,
- Andrew

 

[Renaud Pacalet]

Andrew Mazin wrote:

Hi All,

In my verification module, I am sending packets to the link. To do
this, I am using blocking tasks like this one:

task send_packet;
....
for (i=0; i< packet_length; i=i+1)
@(posedge clk) output = data;
...

Between packets, my module must send idles, starting immediately after
packet and ending just before the new one.
I can define the register which controls idles generations:

task send_packet;
....
disable_idles = 1;
for (i=0; i< packet_length; i=i+1)
@(posedge clk) output = data;
disable_idles = 0;
...


Then, I may use "always" construct to generate idles:

always @(posedge clk)
if (disable_idles == 0)
send_idle;

It will work, but races will occur: disable_idles is written and read
at the same simulation time.

My model must be also able to send packets back-to-back, without idles
between packets.

Is there a way to write this function race-free?
Any help will be highly appreciated

Thanks,
- Andrew

task send_packet;
.....
disable_idles <= 1;
for (i=0; i< packet_length; i=i+1)
@(posedge clk) output = data;
disable_idles <= 0;

is probably what you need. But you have hundreds of different solutions
for this...

Regards,
....
--
Renaud Pacalet, ENST, 46 rue Barrault 75634 Paris Cedex 13
###### Tel. : 01 45 81 78 08 | Fax : 01 45 80 40 36 ######
# Fight Spam! Join EuroCAUCE: http://www.euro.cauce.org/ #

 

[Jim Wu]

You can use the negedge of the clock to update disable_idles.

What does the send_idle task look like? If it is not finished within one
clock cycle, you may have "multiple drivers on the output port" problem.

Jim Wu
jimwu88NOOOSPAM@yahoo.com
http://www.geocities.com/jimwu88/chips/index.html

andrew119@canada.com (Andrew Mazin) wrote in message news:<725b2b95.0308211254.38e2019f@posting.google.com>...

Hi All,

In my verification module, I am sending packets to the link. To do
this, I am using blocking tasks like this one:

task send_packet;
....
for (i=0; i< packet_length; i=i+1)
@(posedge clk) output = data;
...

Between packets, my module must send idles, starting immediately after
packet and ending just before the new one.
I can define the register which controls idles generations:

task send_packet;
....
disable_idles = 1;
for (i=0; i< packet_length; i=i+1)
@(posedge clk) output = data;
disable_idles = 0;
...


Then, I may use "always" construct to generate idles:

always @(posedge clk)
if (disable_idles == 0)
send_idle;

It will work, but races will occur: disable_idles is written and read
at the same simulation time.

My model must be also able to send packets back-to-back, without idles
between packets.

Is there a way to write this function race-free?
Any help will be highly appreciated

Thanks,
- Andrew

 

[Andrew Mazin]

Thanks for all who answered.
Your hints were very helpful.

Regards,
- Andrew

 

[a2zasics]

andrew119@canada.com (Andrew Mazin) wrote in message news:<725b2b95.0308230913.551b6e65@posting.google.com>...

Thanks for all who answered.
Your hints were very helpful.

Regards,
- Andrew

You can try setting this at negative edge, as packets are being sent on positive.

Shardendu