avoid latches

[u_stadler@yahoo.de]

hi

i have to following problem:

i have an array called Storage which goes from 0 to 63:
i fill it from 0 to 3 with a value from outside. after that is done and
my input signal "start" goes high my signal "Index" gets incremented
every clock cycle and with that i want to fill tho other spaces in the
array like that.

the current index place gets filled with:
Storage(Index) <= Storage(Index - 4) xor Storage(Index - 1);

But if i do this i get the warning "Found 8-bit latch for signal".

Can I ignore this or is there any better way to do this?

thanks

 

[Ralf Hildebrandt]

u_stadler@yahoo.de wrote:

But if i do this i get the warning "Found 8-bit latch for signal".

Can I ignore this or is there any better way to do this?

This -as always- depends on what you want to do. A latch is

process(enable,data_in)
begin
if (enable='1') then
latch<=data_in;
end if;
end process;

As you can see it is similar to combinational logic, but the signal
"latch" does not get a value assigned in every possible branch.

If you describe comb. logic and the waring appears, then you did not
cover all possible branches and obviously you modeled something
different than wanted.
If you really need this latch (you need a storage element and you prefer
it rather than flipflops) you should ignore the warning.

Note, that some targets are not capable of latches - many FPGAs do so.
Then you have to find another solution.

Ralf

 

[Hubble]

Can I ignore this or is there any better way to do this?

Nooooo! At least I wouldn't. I do not know exactly what you want to
design, but it sounds something like the following code. Note that it
initializes everything at Reset. This should not produce any latches.
If you forget to set Index at the RESET path, or if you leave out the
RESET path some tools will generate latches.

Hubble.

----- *not tested* ---

SIGNAL Counting: boolean;
SIGNAL Index: natural range 0 to 63;

CNT: PROCESS(RESET,Clock)
BEGIN
IF RESET='1' then
Index<=0; -- do not forget to set index here
Storage<=(others => '0') -- all cells (!)
Counting<=false; -- do not forget to set mode here
ELSIF Rising_Edge(Clock) then
IF Counting=false then
Storage(3 downto 0)<=Input;
END IF;
IF Start='1' THEN
Counting<=true;
Index=4;
END IF;
IF Counting THEN
Storage(Index)<=Storage(Index-4) xor Storage(Index-1);
If Index=63 THEN
Counting<=false;
ELSE
Index<=Index+1;
END IF;
END IF;
END PROCESS CNT;